Change in coreboot[master]: include/cpu/x86/msr: add IA32_ prefix to MC0_ADDR and MC0_MISC

[Felix Held (Code Review)]

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56235 )

Change subject: include/cpu/x86/msr: add IA32_ prefix to MC0_ADDR and MC0_MISC
......................................................................

include/cpu/x86/msr: add IA32_ prefix to MC0_ADDR and MC0_MISC

Those registers are architectural MSR and this also gets them in line
with IA32_MC0_CTL and IA32_MC0_STATUS. Also move them below the
definitions for IA32_MC0_STATUS, so that the numbers of the MSRs are
ascending.

Change-Id: Icef6526c896720248f5b648ddf1a271bdf46917c
Signed-off-by: Felix Held 
---
M src/include/cpu/x86/msr.h
M src/soc/amd/stoneyridge/mca.c
2 files changed, 4 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/56235/1

diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h
index 748aed5..da1932c 100644
--- a/src/include/cpu/x86/msr.h
+++ b/src/include/cpu/x86/msr.h
@@ -74,11 +74,11 @@
 #define  MCA_STATUS_LO_ERRCODE_EXT_SH	16
 #define  MCA_STATUS_LO_ERRCODE_EXT_MASK	(0x3f << MCA_STATUS_LO_ERRCODE_EXT_SH)
 #define  MCA_STATUS_LO_ERRCODE_MASK	(0xffff << 0)
+#define IA32_MC0_ADDR			0x402
+#define IA32_MC0_MISC			0x403
 #define IA32_VMX_BASIC_MSR              0x480
 #define  VMX_BASIC_HI_DUAL_MONITOR      (1UL << (49 - 32))
 #define IA32_VMX_MISC_MSR               0x485
-#define MC0_ADDR			0x402
-#define MC0_MISC			0x403
 #define MC0_CTL_MASK			0xC0010044

#define IA32_PM_ENABLE			0x770
diff --git a/src/soc/amd/stoneyridge/mca.c b/src/soc/amd/stoneyridge/mca.c
index 1523563..c2ec402 100644
--- a/src/soc/amd/stoneyridge/mca.c
+++ b/src/soc/amd/stoneyridge/mca.c
@@ -169,10 +169,10 @@

printk(BIOS_WARNING, "   MC%d_STATUS =   %08x_%08x\n",
    					i, mci.sts.hi, mci.sts.lo);
-				mci.addr = rdmsr(MC0_ADDR + (i * 4));
+				mci.addr = rdmsr(IA32_MC0_ADDR + (i * 4));
    			printk(BIOS_WARNING, "   MC%d_ADDR =     %08x_%08x\n",
    					i, mci.addr.hi, mci.addr.lo);
-				mci.misc = rdmsr(MC0_MISC + (i * 4));
+				mci.misc = rdmsr(IA32_MC0_MISC + (i * 4));
    			printk(BIOS_WARNING, "   MC%d_MISC =     %08x_%08x\n",
    					i, mci.misc.hi, mci.misc.lo);
    			mci.ctl = rdmsr(IA32_MC0_CTL + (i * 4));