Change in coreboot[master]: HACK: soc/mediatek: Add function to raise the CCI frequency

[Yidi Lin (Code Review)]

Hello Weiyi Lu,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/46411

to review the following change.

Change subject: HACK: soc/mediatek: Add function to raise the CCI frequency
......................................................................

HACK: soc/mediatek: Add function to raise the CCI frequency

Implement mt_pll_raise_cci_freq() in MT8192 to raise the frequency.
usage: mt_pll_raise_cci_freq(1400UL * MHz);
note: Obviously, little/big/cci raise_freq() could be merged.

Signed-off-by: Weiyi Lu 
Change-Id: I084cd7888b1dcfdeaef308b8bb3677d034497a30
---
M src/soc/mediatek/common/include/soc/pll_common.h
M src/soc/mediatek/mt8192/pll.c
2 files changed, 28 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/46411/1

diff --git a/src/soc/mediatek/common/include/soc/pll_common.h b/src/soc/mediatek/common/include/soc/pll_common.h
index 54b12e8..59a70ff 100644
--- a/src/soc/mediatek/common/include/soc/pll_common.h
+++ b/src/soc/mediatek/common/include/soc/pll_common.h
@@ -60,6 +60,7 @@
 void mt_pll_init(void);
 void mt_pll_raise_little_cpu_freq(u32 freq);
 void mt_pll_raise_ca76_freq(u32 freq);
+void mt_pll_raise_cci_freq(u32 freq);

enum fmeter_type {
    FMETER_ABIST = 0,
diff --git a/src/soc/mediatek/mt8192/pll.c b/src/soc/mediatek/mt8192/pll.c
index cd65d25..9b13398 100644
--- a/src/soc/mediatek/mt8192/pll.c
+++ b/src/soc/mediatek/mt8192/pll.c
@@ -573,3 +573,30 @@
    /* disable [4] intermediate clock armpll_divider_pll1_ck */
    clrbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 4);
 }
+
+void mt_pll_raise_cci_freq(u32 freq)
+{
+	/* enable [4] intermediate clock armpll_divider_pll1_ck */
+	setbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 4);
+
+	/* switch cci clock source to intermediate clock */
+	clrsetbits32(&mt8192_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK,
+		MCU_MUX_SRC_DIV_PLL1);
+
+	/* disable ccipll frequency output */
+	clrbits32(plls[APMIXED_CCIPLL].reg, PLL_EN);
+
+	/* raise ccipll frequency */
+	pll_set_rate(&plls[APMIXED_CCIPLL], freq);
+
+	/* enable ccipll frequency output */
+	setbits32(plls[APMIXED_CCIPLL].reg, PLL_EN);
+		udelay(PLL_EN_DELAY);
+
+	/* switch cci clock source back to ccipll */
+	clrsetbits32(&mt8192_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK,
+		MCU_MUX_SRC_PLL);
+
+	/* disable [4] intermediate clock armpll_divider_pll1_ck */
+	clrbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 4);
+}

[Paul Menzel (Code Review)]

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46411 )

Change subject: HACK: soc/mediatek: Add function to raise the CCI frequency
......................................................................

Patch Set 6:

(2 comments)

https://review.coreboot.org/c/coreboot/+/46411/6/src/soc/mediatek/mt8192/pll... 
File src/soc/mediatek/mt8192/pll.c:

https://review.coreboot.org/c/coreboot/+/46411/6/src/soc/mediatek/mt8192/pll... 
PS6, Line 600: 		udelay(PLL_EN_DELAY);
Please reduce the indentation by one level.

https://review.coreboot.org/c/coreboot/+/46411/6/src/soc/mediatek/mt8192/pll... 
PS6, Line 604: 		MCU_MUX_SRC_PLL);
Fits on one line in 96 characters?

[pan gao (Code Review)]

pan gao has uploaded a new patch set (#10) to the change originally created by Yidi Lin. ( https://review.coreboot.org/c/coreboot/+/46411 )

Change subject: HACK: soc/mediatek: Add function to raise the CCI frequency
......................................................................

HACK: soc/mediatek: Add function to raise the CCI frequency

Implement mt_pll_raise_cci_freq() in MT8192 to raise the frequency.
usage: mt_pll_raise_cci_freq(1400UL * MHz);
note: Obviously, little/big/cci raise_freq() could be merged.

Signed-off-by: Weiyi Lu 
Change-Id: I084cd7888b1dcfdeaef308b8bb3677d034497a30
---
M src/soc/mediatek/common/include/soc/pll_common.h
M src/soc/mediatek/mt8192/pll.c
2 files changed, 28 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/46411/10

[Yidi Lin (Code Review)]

Hello build bot (Jenkins), Weiyi Lu, pan gao,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/46411

to look at the new patch set (#29).

Change subject: HACK: soc/mediatek: Add function to raise the CCI frequency
......................................................................

HACK: soc/mediatek: Add function to raise the CCI frequency

Implement mt_pll_raise_cci_freq() in MT8192 to raise the frequency.
usage: mt_pll_raise_cci_freq(1400UL * MHz);
note: Obviously, little/big/cci raise_freq() could be merged.

Signed-off-by: Weiyi Lu 
Change-Id: I084cd7888b1dcfdeaef308b8bb3677d034497a30
---
M src/soc/mediatek/common/include/soc/pll_common.h
M src/soc/mediatek/mt8192/pll.c
2 files changed, 28 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/46411/29

Change in coreboot[master]: soc/mediatek/mt8192: Add function to raise the CCI frequency

[Yidi Lin (Code Review)]

Hello Xi Chen, build bot (Jenkins), Weiyi Lu, pan gao,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/46411

to look at the new patch set (#31).

Change subject: soc/mediatek/mt8192: Add function to raise the CCI frequency
......................................................................

soc/mediatek/mt8192: Add function to raise the CCI frequency

Implement mt_pll_raise_cci_freq() in MT8192 to raise the CCI frequency.
Uage: mt_pll_raise_cci_freq(1400UL * MHz);

Signed-off-by: Weiyi Lu 
Change-Id: I084cd7888b1dcfdeaef308b8bb3677d034497a30
---
M src/soc/mediatek/common/include/soc/pll_common.h
M src/soc/mediatek/mt8192/pll.c
2 files changed, 28 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/46411/31

Change in coreboot[master]: soc/mediatek/mt8192: Add function to raise the CCI frequency

[Yidi Lin (Code Review)]

Attention is currently required from: Hung-Te Lin, Yidi Lin.
Hello Hung-Te Lin, Xi Chen, build bot (Jenkins), Weiyi Lu, pan gao,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/46411

to look at the new patch set (#32).

Change subject: soc/mediatek/mt8192: Add function to raise the CCI frequency
......................................................................

soc/mediatek/mt8192: Add function to raise the CCI frequency

Implement mt_pll_raise_cci_freq() in MT8192 to raise the CCI frequency.
Uage: mt_pll_raise_cci_freq(1400UL * MHz);

Signed-off-by: Weiyi Lu 
Change-Id: I084cd7888b1dcfdeaef308b8bb3677d034497a30
---
M src/soc/mediatek/common/include/soc/pll_common.h
M src/soc/mediatek/mt8192/pll.c
2 files changed, 26 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/46411/32

Change in coreboot[master]: soc/mediatek/mt8192: Add function to raise the CCI frequency

[Yidi Lin (Code Review)]

Attention is currently required from: Hung-Te Lin, Paul Menzel.
Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46411 )

Change subject: soc/mediatek/mt8192: Add function to raise the CCI frequency
......................................................................

Patch Set 32:

(2 comments)

File src/soc/mediatek/mt8192/pll.c:

https://review.coreboot.org/c/coreboot/+/46411/comment/fe21a163_909ea704 
PS6, Line 600: 		udelay(PLL_EN_DELAY);
> Please reduce the indentation by one level.

Done

https://review.coreboot.org/c/coreboot/+/46411/comment/3a941578_23e9911f 
PS6, Line 604: 		MCU_MUX_SRC_PLL);
> Fits on one line in 96 characters?

Done

Change in coreboot[master]: soc/mediatek/mt8192: Add function to raise the CCI frequency

[Yu-Ping Wu (Code Review)]

Attention is currently required from: Hung-Te Lin, Paul Menzel, Yidi Lin.
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46411 )

Change subject: soc/mediatek/mt8192: Add function to raise the CCI frequency
......................................................................

Patch Set 33: Code-Review+2

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/46411/comment/f3f0aa77_f1262dde 
PS33, Line 10: Uage
Do you mean "Usage"?

Change in coreboot[master]: soc/mediatek/mt8192: Add function to raise the CCI frequency

[Yidi Lin (Code Review)]

Attention is currently required from: Hung-Te Lin, Paul Menzel, Yidi Lin.
Hello Hung-Te Lin, Xi Chen, build bot (Jenkins), Weiyi Lu, pan gao, Yu-Ping Wu,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/46411

to look at the new patch set (#34).

Change subject: soc/mediatek/mt8192: Add function to raise the CCI frequency
......................................................................

soc/mediatek/mt8192: Add function to raise the CCI frequency

Implement mt_pll_raise_cci_freq() in MT8192 to raise the CCI frequency.
Usage: mt_pll_raise_cci_freq(1400UL * MHz);

Signed-off-by: Weiyi Lu 
Change-Id: I084cd7888b1dcfdeaef308b8bb3677d034497a30
---
M src/soc/mediatek/common/include/soc/pll_common.h
M src/soc/mediatek/mt8192/pll.c
2 files changed, 26 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/46411/34

Change in coreboot[master]: soc/mediatek/mt8192: Add function to raise the CCI frequency

[Yidi Lin (Code Review)]

Attention is currently required from: Hung-Te Lin, Paul Menzel, Yu-Ping Wu.
Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46411 )

Change subject: soc/mediatek/mt8192: Add function to raise the CCI frequency
......................................................................

Patch Set 34:

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/46411/comment/77a9d561_7cc02ab2 
PS33, Line 10: Uage
> Do you mean "Usage"?

Done

Change in coreboot[master]: soc/mediatek/mt8192: Add function to raise the CCI frequency

[Yu-Ping Wu (Code Review)]

Attention is currently required from: Hung-Te Lin, Paul Menzel, Yidi Lin.
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46411 )

Change subject: soc/mediatek/mt8192: Add function to raise the CCI frequency
......................................................................

Patch Set 34: Code-Review+2

Change in coreboot[master]: soc/mediatek/mt8192: Add function to raise the CCI frequency

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46411 )

Change subject: soc/mediatek/mt8192: Add function to raise the CCI frequency
......................................................................

soc/mediatek/mt8192: Add function to raise the CCI frequency

Implement mt_pll_raise_cci_freq() in MT8192 to raise the CCI frequency.
Usage: mt_pll_raise_cci_freq(1400UL * MHz);

Signed-off-by: Weiyi Lu 
Change-Id: I084cd7888b1dcfdeaef308b8bb3677d034497a30
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46411
Tested-by: build bot (Jenkins) 
Reviewed-by: Yu-Ping Wu 
---
M src/soc/mediatek/common/include/soc/pll_common.h
M src/soc/mediatek/mt8192/pll.c
2 files changed, 26 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Yu-Ping Wu: Looks good to me, approved

diff --git a/src/soc/mediatek/common/include/soc/pll_common.h b/src/soc/mediatek/common/include/soc/pll_common.h
index ae6ad64..cb22796 100644
--- a/src/soc/mediatek/common/include/soc/pll_common.h
+++ b/src/soc/mediatek/common/include/soc/pll_common.h
@@ -69,6 +69,7 @@
 int pll_set_rate(const struct pll *pll, u32 rate);
 void mt_pll_init(void);
 void mt_pll_raise_little_cpu_freq(u32 freq);
+void mt_pll_raise_cci_freq(u32 freq);

enum fmeter_type {
    FMETER_ABIST = 0,
diff --git a/src/soc/mediatek/mt8192/pll.c b/src/soc/mediatek/mt8192/pll.c
index 6d61fb4..f0a9509 100644
--- a/src/soc/mediatek/mt8192/pll.c
+++ b/src/soc/mediatek/mt8192/pll.c
@@ -559,3 +559,28 @@

return 0;
 }
+
+void mt_pll_raise_cci_freq(u32 freq)
+{
+	/* enable [4] intermediate clock armpll_divider_pll1_ck */
+	setbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 4);
+
+	/* switch cci clock source to intermediate clock */
+	clrsetbits32(&mt8192_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_DIV_PLL1);
+
+	/* disable ccipll frequency output */
+	clrbits32(plls[APMIXED_CCIPLL].reg, PLL_EN);
+
+	/* raise ccipll frequency */
+	pll_set_rate(&plls[APMIXED_CCIPLL], freq);
+
+	/* enable ccipll frequency output */
+	setbits32(plls[APMIXED_CCIPLL].reg, PLL_EN);
+	udelay(PLL_EN_DELAY);
+
+	/* switch cci clock source back to ccipll */
+	clrsetbits32(&mt8192_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_PLL);
+
+	/* disable [4] intermediate clock armpll_divider_pll1_ck */
+	clrbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 4);
+}