Change in coreboot[master]: soc/skylake: lock aesni msr

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Michael Niewöhner (Code Review)

1 Sep 2019 1 Sep '19

2:49 p.m.

Michael Niewöhner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35188 )

Change subject: soc/skylake: lock aesni msr ......................................................................

soc/skylake: lock aesni msr

Change-Id: I97a0d3b1b9b0452e929ca07d29c03237b413e521 Signed-off-by: Michael Niewöhner foss@mniewoehner.de --- M src/soc/intel/skylake/cpu.c 1 file changed, 13 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/35188/1

diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 0d49d28..984c134 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -420,6 +420,16 @@ wrmsr(MSR_EMULATE_PM_TIMER, msr); }

+void cpu_lock_aesni(void) { + msr_t msr; + + msr = rdmsr(MSR_FEATURE_CONFIG); + if ((msr.lo & 1) == 0) { + msr.lo |= 1; /* Lock it */ + wrmsr(MSR_FEATURE_CONFIG, msr); + } +} + /* All CPUs including BSP will run the following function. */ void soc_core_init(struct device *cpu) { @@ -442,6 +452,9 @@ /* Configure Intel Speed Shift */ configure_isst();

+ /* Lock AES-NI MSR */ + cpu_lock_aesni(); + /* Enable ACPI Timer Emulation via MSR 0x121 */ enable_pm_timer_emulation();

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build bot (Jenkins) (Code Review)

1 Sep 1 Sep

2:49 p.m.

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35188 )

Change subject: soc/skylake: lock aesni msr ......................................................................

Patch Set 1:

(2 comments)

https://review.coreboot.org/c/coreboot/+/35188/1/src/soc/intel/skylake/cpu.c File src/soc/intel/skylake/cpu.c:

https://review.coreboot.org/c/coreboot/+/35188/1/src/soc/intel/skylake/cpu.c... PS1, Line 423: void cpu_lock_aesni(void) { open brace '{' following function definitions go on the next line

https://review.coreboot.org/c/coreboot/+/35188/1/src/soc/intel/skylake/cpu.c... PS1, Line 432: trailing whitespace

Michael Niewöhner (Code Review)

2:52 p.m.

Hello Patrick Rudolph, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/35188

to look at the new patch set (#2).

Change subject: soc/skylake: lock aesni msr ......................................................................

soc/skylake: lock aesni msr

Change-Id: I97a0d3b1b9b0452e929ca07d29c03237b413e521 Signed-off-by: Michael Niewöhner foss@mniewoehner.de --- M src/soc/intel/skylake/cpu.c 1 file changed, 14 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/35188/2

build bot (Jenkins) (Code Review)

2:52 p.m.

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35188 )

Change subject: soc/skylake: lock aesni msr ......................................................................

Patch Set 2:

(1 comment)

https://review.coreboot.org/c/coreboot/+/35188/2/src/soc/intel/skylake/cpu.c File src/soc/intel/skylake/cpu.c:

https://review.coreboot.org/c/coreboot/+/35188/2/src/soc/intel/skylake/cpu.c... PS2, Line 433: trailing whitespace

Michael Niewöhner (Code Review)

3:14 p.m.

Hello Patrick Rudolph, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/35188

to look at the new patch set (#3).

Change subject: soc/skylake: lock aesni msr ......................................................................

soc/skylake: lock aesni msr

Change-Id: I97a0d3b1b9b0452e929ca07d29c03237b413e521 Signed-off-by: Michael Niewöhner foss@mniewoehner.de --- M src/soc/intel/skylake/cpu.c 1 file changed, 14 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/35188/3

build bot (Jenkins) (Code Review)

3:15 p.m.

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35188 )

Change subject: soc/skylake: lock aesni msr ......................................................................

Patch Set 3:

(1 comment)

https://review.coreboot.org/c/coreboot/+/35188/3/src/soc/intel/skylake/cpu.c File src/soc/intel/skylake/cpu.c:

https://review.coreboot.org/c/coreboot/+/35188/3/src/soc/intel/skylake/cpu.c... PS3, Line 433: trailing whitespace

Michael Niewöhner (Code Review)

3:56 p.m.

Hello Patrick Rudolph, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/35188

to look at the new patch set (#4).

Change subject: soc/skylake: lock aesni msr ......................................................................

soc/skylake: lock aesni msr

Change-Id: I97a0d3b1b9b0452e929ca07d29c03237b413e521 Signed-off-by: Michael Niewöhner foss@mniewoehner.de --- M src/soc/intel/skylake/cpu.c 1 file changed, 14 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/35188/4

Angel Pons (Code Review)

10:41 p.m.

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35188 )

Change subject: soc/skylake: lock aesni msr ......................................................................

Patch Set 4:

(2 comments)

https://review.coreboot.org/c/coreboot/+/35188/4//COMMIT_MSG Commit Message:

https://review.coreboot.org/c/coreboot/+/35188/4//COMMIT_MSG@7 PS4, Line 7: msr MSR

https://review.coreboot.org/c/coreboot/+/35188/4/src/soc/intel/skylake/cpu.c File src/soc/intel/skylake/cpu.c:

https://review.coreboot.org/c/coreboot/+/35188/4/src/soc/intel/skylake/cpu.c... PS4, Line 429: /* Lock it */ This comment is really obnoxious... maybe explain what locking this is useful for?

Michael Niewöhner (Code Review)

11:07 p.m.

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35188 )

Change subject: soc/skylake: lock aesni msr ......................................................................

Patch Set 4:

(1 comment)

https://review.coreboot.org/c/coreboot/+/35188/4/src/soc/intel/skylake/cpu.c File src/soc/intel/skylake/cpu.c:

https://review.coreboot.org/c/coreboot/+/35188/4/src/soc/intel/skylake/cpu.c... PS4, Line 429: /* Lock it */

...

This comment is really obnoxious... […]

... copied from somewhere below, you can find that multiple times in that file;) Maybe something like "Lock it because the datasheet says so" or "Lock it to prevent unintended disabling" ?

Michael Niewöhner (Code Review)

11:09 p.m.

New subject: Change in coreboot[master]: soc/skylake: lock AES-NI MSR

Hello Patrick Rudolph, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/35188

to look at the new patch set (#5).

Change subject: soc/skylake: lock AES-NI MSR ......................................................................

soc/skylake: lock AES-NI MSR

Lock AES-NI register to prevent uninteded disabling, as suggested by the MSR datasheet.

Change-Id: I97a0d3b1b9b0452e929ca07d29c03237b413e521 Signed-off-by: Michael Niewöhner foss@mniewoehner.de --- M src/soc/intel/skylake/cpu.c 1 file changed, 15 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/35188/5

Furquan Shaikh (Code Review)

2 Sep 2 Sep

6:05 a.m.

New subject: Change in coreboot[master]: soc/skylake: lock AES-NI MSR

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35188 )

Change subject: soc/skylake: lock AES-NI MSR ......................................................................

Patch Set 5:

(1 comment)

https://review.coreboot.org/c/coreboot/+/35188/5/src/soc/intel/skylake/cpu.c File src/soc/intel/skylake/cpu.c:

https://review.coreboot.org/c/coreboot/+/35188/5/src/soc/intel/skylake/cpu.c... PS5, Line 428: MSR_FEATURE_CONFIG Before reading the MSR, don't you need to check CPUID to determine if the MSR is really supported?

Michael Niewöhner (Code Review)

3 Sep 3 Sep

11:49 a.m.

New subject: Change in coreboot[master]: soc/skylake: lock AES-NI MSR

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35188 )

Change subject: soc/skylake: lock AES-NI MSR ......................................................................

Patch Set 5:

(1 comment)

https://review.coreboot.org/c/coreboot/+/35188/5/src/soc/intel/skylake/cpu.c File src/soc/intel/skylake/cpu.c:

https://review.coreboot.org/c/coreboot/+/35188/5/src/soc/intel/skylake/cpu.c... PS5, Line 428: MSR_FEATURE_CONFIG

...

Before reading the MSR, don't you need to check CPUID to determine if the MSR is really supported?

No, on skylake and it's successors this is always supported

-- To view, visit https://review.coreboot.org/c/coreboot/+/35188 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I97a0d3b1b9b0452e929ca07d29c03237b413e521 Gerrit-Change-Number: 35188 Gerrit-PatchSet: 5 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Angel Pons th3fanbus@gmail.com Gerrit-CC: Furquan Shaikh furquan@google.com Gerrit-Comment-Date: Tue, 03 Sep 2019 11:49:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh furquan@google.com Gerrit-MessageType: comment

Michael Niewöhner (Code Review)

4 Sep 4 Sep

5:06 p.m.

New subject: Change in coreboot[master]: soc/skylake: lock AES-NI MSR

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35188 )

Change subject: soc/skylake: lock AES-NI MSR ......................................................................

Patch Set 5:

(1 comment)

https://review.coreboot.org/c/coreboot/+/35188/5/src/soc/intel/skylake/cpu.c File src/soc/intel/skylake/cpu.c:

https://review.coreboot.org/c/coreboot/+/35188/5/src/soc/intel/skylake/cpu.c... PS5, Line 428: MSR_FEATURE_CONFIG

...

No, on skylake and it's successors this is always supported

Done

-- To view, visit https://review.coreboot.org/c/coreboot/+/35188 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I97a0d3b1b9b0452e929ca07d29c03237b413e521 Gerrit-Change-Number: 35188 Gerrit-PatchSet: 5 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Angel Pons th3fanbus@gmail.com Gerrit-CC: Furquan Shaikh furquan@google.com Gerrit-Comment-Date: Wed, 04 Sep 2019 17:06:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michael Niewöhner Comment-In-Reply-To: Furquan Shaikh furquan@google.com Gerrit-MessageType: comment

Michael Niewöhner (Code Review)

5 Sep 5 Sep

10:45 p.m.

New subject: Change in coreboot[master]: soc/skylake: lock AES-NI MSR

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35188 )

Change subject: soc/skylake: lock AES-NI MSR ......................................................................

Patch Set 5:

(2 comments)

https://review.coreboot.org/c/coreboot/+/35188/4//COMMIT_MSG Commit Message:

https://review.coreboot.org/c/coreboot/+/35188/4//COMMIT_MSG@7 PS4, Line 7: msr

...

MSR

Done

https://review.coreboot.org/c/coreboot/+/35188/4/src/soc/intel/skylake/cpu.c File src/soc/intel/skylake/cpu.c:

https://review.coreboot.org/c/coreboot/+/35188/4/src/soc/intel/skylake/cpu.c... PS4, Line 429: /* Lock it */

...

... […]

Done

-- To view, visit https://review.coreboot.org/c/coreboot/+/35188 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I97a0d3b1b9b0452e929ca07d29c03237b413e521 Gerrit-Change-Number: 35188 Gerrit-PatchSet: 5 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Angel Pons th3fanbus@gmail.com Gerrit-CC: Furquan Shaikh furquan@google.com Gerrit-Comment-Date: Thu, 05 Sep 2019 22:45:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons th3fanbus@gmail.com Comment-In-Reply-To: Michael Niewöhner Gerrit-MessageType: comment

Michael Niewöhner (Code Review)

19 Sep 19 Sep

3:26 p.m.

New subject: Change in coreboot[master]: soc/skylake: lock AES-NI MSR

Hello Patrick Rudolph, Subrata Banik, Angel Pons, build bot (Jenkins), Furquan Shaikh,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/35188

to look at the new patch set (#6).

Change subject: soc/skylake: lock AES-NI MSR ......................................................................

soc/skylake: lock AES-NI MSR

Lock AES-NI register to prevent uninteded disabling, as suggested by the MSR datasheet.

Tested on X11SSM-F

Change-Id: I97a0d3b1b9b0452e929ca07d29c03237b413e521 Signed-off-by: Michael Niewöhner foss@mniewoehner.de --- M src/soc/intel/skylake/cpu.c 1 file changed, 15 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/35188/6

Michael Niewöhner (Code Review)

21 Sep 21 Sep

9:24 p.m.

New subject: Change in coreboot[master]: soc/skylake: lock AES-NI MSR

Hello Patrick Rudolph, Subrata Banik, Angel Pons, build bot (Jenkins), Furquan Shaikh,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/35188

to look at the new patch set (#7).

Change subject: soc/skylake: lock AES-NI MSR ......................................................................

soc/skylake: lock AES-NI MSR

Lock AES-NI register to prevent uninteded disabling, as suggested by the MSR datasheet.

Change-Id: I97a0d3b1b9b0452e929ca07d29c03237b413e521 Signed-off-by: Michael Niewöhner foss@mniewoehner.de --- M src/soc/intel/skylake/cpu.c 1 file changed, 15 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/35188/7

Michael Niewöhner (Code Review)

10:09 p.m.

New subject: Change in coreboot[master]: soc/skylake: lock AES-NI MSR

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35188 )

Change subject: soc/skylake: lock AES-NI MSR ......................................................................

Patch Set 7:

*ping* ;-) Any comments on this?

-- To view, visit https://review.coreboot.org/c/coreboot/+/35188 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I97a0d3b1b9b0452e929ca07d29c03237b413e521 Gerrit-Change-Number: 35188 Gerrit-PatchSet: 7 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com Gerrit-Reviewer: Furquan Shaikh furquan@google.com Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber nico.h@gmx.de Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: Subrata Banik subrata.banik@intel.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-Comment-Date: Sat, 21 Sep 2019 22:09:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

Subrata Banik (Code Review)

22 Sep 22 Sep

4:05 a.m.

New subject: Change in coreboot[master]: soc/skylake: lock AES-NI MSR

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35188 )

Change subject: soc/skylake: lock AES-NI MSR ......................................................................

Patch Set 7:

(2 comments)

https://review.coreboot.org/c/coreboot/+/35188/7//COMMIT_MSG Commit Message:

https://review.coreboot.org/c/coreboot/+/35188/7//COMMIT_MSG@6 PS7, Line 6: : soc/skylake soc/intel/skylake ?

https://review.coreboot.org/c/coreboot/+/35188/7//COMMIT_MSG@10 PS7, Line 10: MSR datasheet. any idea on whats been the issue if not getting lock ?

-- To view, visit https://review.coreboot.org/c/coreboot/+/35188 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I97a0d3b1b9b0452e929ca07d29c03237b413e521 Gerrit-Change-Number: 35188 Gerrit-PatchSet: 7 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com Gerrit-Reviewer: Furquan Shaikh furquan@google.com Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber nico.h@gmx.de Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: Subrata Banik subrata.banik@intel.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-Comment-Date: Sun, 22 Sep 2019 04:05:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

Michael Niewöhner (Code Review)

8:28 a.m.

New subject: Change in coreboot[master]: soc/intel/skylake: lock AES-NI MSR

Hello Patrick Rudolph, Subrata Banik, Angel Pons, build bot (Jenkins), Nico Huber, Patrick Georgi, Furquan Shaikh,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/35188

to look at the new patch set (#8).

Change subject: soc/intel/skylake: lock AES-NI MSR ......................................................................

soc/intel/skylake: lock AES-NI MSR

Lock AES-NI register to prevent unintended disabling, as suggested by the MSR datasheet.

Change-Id: I97a0d3b1b9b0452e929ca07d29c03237b413e521 Signed-off-by: Michael Niewöhner foss@mniewoehner.de --- M src/soc/intel/skylake/cpu.c 1 file changed, 15 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/35188/8

-- To view, visit https://review.coreboot.org/c/coreboot/+/35188 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I97a0d3b1b9b0452e929ca07d29c03237b413e521 Gerrit-Change-Number: 35188 Gerrit-PatchSet: 8 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com Gerrit-Reviewer: Furquan Shaikh furquan@google.com Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber nico.h@gmx.de Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: Subrata Banik subrata.banik@intel.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-MessageType: newpatchset

Michael Niewöhner (Code Review)

8:28 a.m.

New subject: Change in coreboot[master]: soc/intel/skylake: lock AES-NI MSR

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35188 )

Change subject: soc/intel/skylake: lock AES-NI MSR ......................................................................

Patch Set 8:

(2 comments)

https://review.coreboot.org/c/coreboot/+/35188/7//COMMIT_MSG Commit Message:

https://review.coreboot.org/c/coreboot/+/35188/7//COMMIT_MSG@6 PS7, Line 6: : soc/skylake

...

soc/intel/skylake ?

Done

https://review.coreboot.org/c/coreboot/+/35188/7//COMMIT_MSG@10 PS7, Line 10: MSR datasheet.

...

any idea on whats been the issue if not getting lock ?

uhm, it could be disabled unintended...

-- To view, visit https://review.coreboot.org/c/coreboot/+/35188 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I97a0d3b1b9b0452e929ca07d29c03237b413e521 Gerrit-Change-Number: 35188 Gerrit-PatchSet: 8 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com Gerrit-Reviewer: Furquan Shaikh furquan@google.com Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber nico.h@gmx.de Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: Subrata Banik subrata.banik@intel.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-Comment-Date: Sun, 22 Sep 2019 08:28:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik subrata.banik@intel.com Gerrit-MessageType: comment

Michael Niewöhner (Code Review)

8:34 a.m.

New subject: Change in coreboot[master]: soc/intel/skylake: lock AES-NI MSR

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35188 )

Change subject: soc/intel/skylake: lock AES-NI MSR ......................................................................

Patch Set 8:

(1 comment)

https://review.coreboot.org/c/coreboot/+/35188/7//COMMIT_MSG Commit Message:

https://review.coreboot.org/c/coreboot/+/35188/7//COMMIT_MSG@10 PS7, Line 10: MSR datasheet.

...

uhm, it could be disabled unintended...

the same is done in src/soc/intel/apollolake/cpu.c

-- To view, visit https://review.coreboot.org/c/coreboot/+/35188 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I97a0d3b1b9b0452e929ca07d29c03237b413e521 Gerrit-Change-Number: 35188 Gerrit-PatchSet: 8 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com Gerrit-Reviewer: Furquan Shaikh furquan@google.com Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber nico.h@gmx.de Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: Subrata Banik subrata.banik@intel.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-Comment-Date: Sun, 22 Sep 2019 08:34:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik subrata.banik@intel.com Comment-In-Reply-To: Michael Niewöhner Gerrit-MessageType: comment

Michael Niewöhner (Code Review)

23 Sep 23 Sep

9:20 a.m.

New subject: Change in coreboot[master]: soc/intel/skylake: lock AES-NI MSR

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35188 )

Change subject: soc/intel/skylake: lock AES-NI MSR ......................................................................

Patch Set 8:

(1 comment)

https://review.coreboot.org/c/coreboot/+/35188/7//COMMIT_MSG Commit Message:

https://review.coreboot.org/c/coreboot/+/35188/7//COMMIT_MSG@10 PS7, Line 10: MSR datasheet.

...

the same is done in src/soc/intel/apollolake/cpu. […]

Done

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Paul Menzel (Code Review)

12:25 p.m.

New subject: Change in coreboot[master]: soc/intel/skylake: lock AES-NI MSR

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35188 )

Change subject: soc/intel/skylake: lock AES-NI MSR ......................................................................

Patch Set 8: Code-Review+1

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Michael Niewöhner (Code Review)

10:28 p.m.

New subject: Change in coreboot[master]: soc/intel/skylake: lock AES-NI MSR

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35188 )

Change subject: soc/intel/skylake: lock AES-NI MSR ......................................................................

Patch Set 8: Code-Review+1

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Michael Niewöhner (Code Review)

10:28 p.m.

New subject: Change in coreboot[master]: soc/intel/skylake: lock AES-NI MSR

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35188 )

Change subject: soc/intel/skylake: lock AES-NI MSR ......................................................................

Patch Set 8: -Code-Review

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Furquan Shaikh (Code Review)

24 Sep 24 Sep

4:12 a.m.

New subject: Change in coreboot[master]: soc/intel/skylake: lock AES-NI MSR

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35188 )

Change subject: soc/intel/skylake: lock AES-NI MSR ......................................................................

Patch Set 8:

(1 comment)

https://review.coreboot.org/c/coreboot/+/35188/7//COMMIT_MSG Commit Message:

https://review.coreboot.org/c/coreboot/+/35188/7//COMMIT_MSG@10 PS7, Line 10: MSR datasheet.

...

Done

Is the disabling happening in coreboot or is it some other component?

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Michael Niewöhner (Code Review)

11:04 a.m.

New subject: Change in coreboot[master]: soc/intel/skylake: lock AES-NI MSR

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35188 )

Change subject: soc/intel/skylake: lock AES-NI MSR ......................................................................

Patch Set 8:

(1 comment)

https://review.coreboot.org/c/coreboot/+/35188/7//COMMIT_MSG Commit Message:

https://review.coreboot.org/c/coreboot/+/35188/7//COMMIT_MSG@10 PS7, Line 10: MSR datasheet.

...

Is the disabling happening in coreboot or is it some other component?

Sorry, what is the question here? it's an MSR

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Furquan Shaikh (Code Review)

5:11 p.m.

New subject: Change in coreboot[master]: soc/intel/skylake: lock AES-NI MSR

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35188 )

Change subject: soc/intel/skylake: lock AES-NI MSR ......................................................................

Patch Set 8:

(1 comment)

https://review.coreboot.org/c/coreboot/+/35188/7//COMMIT_MSG Commit Message:

https://review.coreboot.org/c/coreboot/+/35188/7//COMMIT_MSG@10 PS7, Line 10: MSR datasheet.

...

Sorry, what is the question here? it's an MSR

You mentioned that this locking is being done to avoid "unintended disabling". What component is doing the unintended disabling? Is that something you observed in practice? Or is this locking being done just as a precaution?

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Michael Niewöhner (Code Review)

7:10 p.m.

New subject: Change in coreboot[master]: soc/intel/skylake: lock AES-NI MSR

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35188 )

Change subject: soc/intel/skylake: lock AES-NI MSR ......................................................................

Patch Set 8:

(1 comment)

https://review.coreboot.org/c/coreboot/+/35188/7//COMMIT_MSG Commit Message:

https://review.coreboot.org/c/coreboot/+/35188/7//COMMIT_MSG@10 PS7, Line 10: MSR datasheet.

...

You mentioned that this locking is being done to avoid "unintended disabling". […]

Ah, well, this is done as precaution

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Furquan Shaikh (Code Review)

7:26 p.m.

New subject: Change in coreboot[master]: soc/intel/skylake: lock AES-NI MSR

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35188 )

Change subject: soc/intel/skylake: lock AES-NI MSR ......................................................................

Patch Set 8: Code-Review+2

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Patrick Rudolph (Code Review)

25 Sep 25 Sep

6:15 a.m.

New subject: Change in coreboot[master]: soc/intel/skylake: lock AES-NI MSR

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35188 )

Change subject: soc/intel/skylake: lock AES-NI MSR ......................................................................

Patch Set 8: Code-Review-1

According to https://github.com/tianocore/edk2/blob/master/UefiCpuPkg/Library/CpuCommonFe... this should only be written on thread0 of each core. I've to check additional documentation, but it looks like this could #GP on HT enabled platforms. This check should be done for all SoCs, for all MSR accesses in MP init.

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Furquan Shaikh (Code Review)

6:16 a.m.

New subject: Change in coreboot[master]: soc/intel/skylake: lock AES-NI MSR

Furquan Shaikh has removed a vote from this change. ( https://review.coreboot.org/c/coreboot/+/35188 )

Change subject: soc/intel/skylake: lock AES-NI MSR ......................................................................

Removed Code-Review+2 by Furquan Shaikh furquan@google.com

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Subrata Banik (Code Review)

6:24 a.m.

New subject: Change in coreboot[master]: soc/intel/skylake: lock AES-NI MSR

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35188 )

Change subject: soc/intel/skylake: lock AES-NI MSR ......................................................................

Patch Set 8:

...

Patch Set 8: Code-Review-1

According to https://github.com/tianocore/edk2/blob/master/UefiCpuPkg/Library/CpuCommonFe... this should only be written on thread0 of each core. I've to check additional documentation, but it looks like this could #GP on HT enabled platforms. This check should be done for all SoCs, for all MSR accesses in MP init.

Thanks Patrick for pointing out, thats the reason i have asked what problem we are seeing if we like to set this msr then right place might be cpu.c where we are running feature programming

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Patrick Rudolph (Code Review)

7:03 a.m.

New subject: Change in coreboot[master]: soc/intel/skylake: lock AES-NI MSR

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35188 )

Change subject: soc/intel/skylake: lock AES-NI MSR ......................................................................

Patch Set 8:

Intel SDM https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-3... lists that MSR as "Core", not as "Thread". You need to call intel_ht_sibling() or something similar to run it once on every core (I'm looking for a good code example, but can't find it ...).

That might also be the culprit of crashing SGX init with HT enabled...

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Michael Niewöhner (Code Review)

9:55 a.m.

New subject: Change in coreboot[master]: soc/intel/skylake: lock AES-NI MSR

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35188 )

Change subject: soc/intel/skylake: lock AES-NI MSR ......................................................................

Patch Set 8:

(1 comment)

...

Patch Set 8:

Intel SDM https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-3... lists that MSR as "Core", not as "Thread". You need to call intel_ht_sibling() or something similar to run it once on every core (I'm looking for a good code example, but can't find it ...).

That might also be the culprit of crashing SGX init with HT enabled...

Thank you, I will look into this later this day and test SGX+HT again then

https://review.coreboot.org/c/coreboot/+/35188/7//COMMIT_MSG Commit Message:

https://review.coreboot.org/c/coreboot/+/35188/7//COMMIT_MSG@10 PS7, Line 10: MSR datasheet.

...

Ah, well, this is done as precaution

Done

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Michael Niewöhner (Code Review)

1 Oct 1 Oct

8:49 p.m.

New subject: Change in coreboot[master]: soc/intel/skylake: lock AES-NI MSR

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35188 )

Change subject: soc/intel/skylake: lock AES-NI MSR ......................................................................

Patch Set 9:

This change is ready for review.

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Michael Niewöhner (Code Review)

8:53 p.m.

New subject: Change in coreboot[master]: soc/intel/skylake: lock AES-NI MSR

Hello Patrick Rudolph, Subrata Banik, Angel Pons, Paul Menzel, build bot (Jenkins), Nico Huber, Furquan Shaikh, Patrick Georgi,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/35188

to look at the new patch set (#10).

Change subject: soc/intel/skylake: lock AES-NI MSR ......................................................................

soc/intel/skylake: lock AES-NI MSR

Lock AES-NI register to prevent unintended disabling, as suggested by the MSR datasheet.

Change-Id: I97a0d3b1b9b0452e929ca07d29c03237b413e521 Signed-off-by: Michael Niewöhner foss@mniewoehner.de --- M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/cpu.c 2 files changed, 22 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/35188/10

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Patrick Rudolph (Code Review)

2 Oct 2 Oct

8:54 a.m.

New subject: Change in coreboot[master]: soc/intel/skylake: lock AES-NI MSR

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35188 )

Change subject: soc/intel/skylake: lock AES-NI MSR ......................................................................

Patch Set 10: Code-Review+1

Needs test.

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Michael Niewöhner (Code Review)

3:34 p.m.

New subject: Change in coreboot[master]: soc/intel/skylake: lock AES-NI MSR

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35188 )

Change subject: soc/intel/skylake: lock AES-NI MSR ......................................................................

Patch Set 10:

(1 comment)

https://review.coreboot.org/c/coreboot/+/35188/9/src/soc/intel/skylake/cpu.c File src/soc/intel/skylake/cpu.c:

https://review.coreboot.org/c/coreboot/+/35188/9/src/soc/intel/skylake/cpu.c... PS9, Line 462: if (!intel_ht_sibling()) {

...

braces {} are not necessary for single statement blocks

Done

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Michael Niewöhner (Code Review)

21 Oct 21 Oct

9:59 p.m.

New subject: Change in coreboot[master]: soc/intel/skylake: lock AES-NI MSR

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35188 )

Change subject: soc/intel/skylake: lock AES-NI MSR ......................................................................

Patch Set 10:

ping.

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Nico Huber (Code Review)

23 Oct 23 Oct

8:06 p.m.

New subject: Change in coreboot[master]: soc/intel/skylake: lock AES-NI MSR

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35188 )

Change subject: soc/intel/skylake: lock AES-NI MSR ......................................................................

Patch Set 10: Code-Review+1

(1 comment)

https://review.coreboot.org/c/coreboot/+/35188/10/src/soc/intel/skylake/cpu.... File src/soc/intel/skylake/cpu.c:

https://review.coreboot.org/c/coreboot/+/35188/10/src/soc/intel/skylake/cpu.... PS10, Line 423: /* Lock AES-NI (MSR_FEATURE_CONFIG) to prevent unintended disabling as suggested in Intel Please add a line break after the /*

Also, the line could be broken earlier to enhance readability.

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Michael Niewöhner (Code Review)

8:16 p.m.

New subject: Change in coreboot[master]: soc/intel/skylake: lock AES-NI MSR

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35188 )

Change subject: soc/intel/skylake: lock AES-NI MSR ......................................................................

Uploaded patch set 11: Commit message was updated.

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Michael Niewöhner (Code Review)

8:16 p.m.

New subject: Change in coreboot[master]: soc/intel/skylake: lock AES-NI MSR

Hello Patrick Rudolph, Subrata Banik, Angel Pons, Paul Menzel, build bot (Jenkins), Nico Huber, Furquan Shaikh, Patrick Georgi,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/35188

to look at the new patch set (#11).

Change subject: soc/intel/skylake: lock AES-NI MSR ......................................................................

soc/intel/skylake: lock AES-NI MSR

Lock AES-NI register to prevent unintended disabling, as suggested by the MSR datasheet.

Successfully tested by reading the MSR on X11SSM-F

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/35188/11

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Michael Niewöhner (Code Review)

8:17 p.m.

New subject: Change in coreboot[master]: soc/intel/skylake: lock AES-NI MSR

Hello Patrick Rudolph, Subrata Banik, Angel Pons, Paul Menzel, build bot (Jenkins), Nico Huber, Furquan Shaikh, Patrick Georgi,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/35188

to look at the new patch set (#12).

Change subject: soc/intel/skylake: lock AES-NI MSR ......................................................................

soc/intel/skylake: lock AES-NI MSR

Lock AES-NI register to prevent unintended disabling, as suggested by the MSR datasheet.

Successfully tested by reading the MSR on X11SSM-F

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/35188/12

-- To view, visit https://review.coreboot.org/c/coreboot/+/35188 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I97a0d3b1b9b0452e929ca07d29c03237b413e521 Gerrit-Change-Number: 35188 Gerrit-PatchSet: 12 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com Gerrit-Reviewer: Furquan Shaikh furquan@google.com Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber nico.h@gmx.de Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Reviewer: Subrata Banik subrata.banik@intel.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-MessageType: newpatchset

Michael Niewöhner (Code Review)

8:17 p.m.

New subject: Change in coreboot[master]: soc/intel/skylake: lock AES-NI MSR

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35188 )

Change subject: soc/intel/skylake: lock AES-NI MSR ......................................................................

Uploaded patch set 12.

-- To view, visit https://review.coreboot.org/c/coreboot/+/35188 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I97a0d3b1b9b0452e929ca07d29c03237b413e521 Gerrit-Change-Number: 35188 Gerrit-PatchSet: 12 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com Gerrit-Reviewer: Furquan Shaikh furquan@google.com Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber nico.h@gmx.de Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Reviewer: Subrata Banik subrata.banik@intel.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-Comment-Date: Wed, 23 Oct 2019 20:17:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

Michael Niewöhner (Code Review)

8:17 p.m.

New subject: Change in coreboot[master]: soc/intel/skylake: lock AES-NI MSR

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35188 )

Change subject: soc/intel/skylake: lock AES-NI MSR ......................................................................

Patch Set 12:

(1 comment)

https://review.coreboot.org/c/coreboot/+/35188/10/src/soc/intel/skylake/cpu.... File src/soc/intel/skylake/cpu.c:

https://review.coreboot.org/c/coreboot/+/35188/10/src/soc/intel/skylake/cpu.... PS10, Line 423: /* Lock AES-NI (MSR_FEATURE_CONFIG) to prevent unintended disabling as suggested in Intel

...

Please add a line break after the /* […]

Done

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Nico Huber (Code Review)

8:24 p.m.

New subject: Change in coreboot[master]: soc/intel/skylake: lock AES-NI MSR

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35188 )

Change subject: soc/intel/skylake: lock AES-NI MSR ......................................................................

Patch Set 12: Code-Review+2

-- To view, visit https://review.coreboot.org/c/coreboot/+/35188 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I97a0d3b1b9b0452e929ca07d29c03237b413e521 Gerrit-Change-Number: 35188 Gerrit-PatchSet: 12 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com Gerrit-Reviewer: Furquan Shaikh furquan@google.com Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber nico.h@gmx.de Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Reviewer: Subrata Banik subrata.banik@intel.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-Comment-Date: Wed, 23 Oct 2019 20:24:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

Patrick Georgi (Code Review)

8:39 p.m.

New subject: Change in coreboot[master]: soc/intel/skylake: lock AES-NI MSR

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/35188 )

Change subject: soc/intel/skylake: lock AES-NI MSR ......................................................................

soc/intel/skylake: lock AES-NI MSR

Lock AES-NI register to prevent unintended disabling, as suggested by the MSR datasheet.

Successfully tested by reading the MSR on X11SSM-F

Change-Id: I97a0d3b1b9b0452e929ca07d29c03237b413e521 Signed-off-by: Michael Niewöhner foss@mniewoehner.de Reviewed-on: https://review.coreboot.org/c/coreboot/+/35188 Reviewed-by: Patrick Georgi pgeorgi@google.com Reviewed-by: Nico Huber nico.h@gmx.de Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/cpu.c 2 files changed, 23 insertions(+), 0 deletions(-)

Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved Nico Huber: Looks good to me, approved

diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 901e5f9..8bdd9b5 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -31,6 +31,7 @@ select COMMON_FADT select CPU_INTEL_COMMON select CPU_INTEL_FIRMWARE_INTERFACE_TABLE + select CPU_INTEL_COMMON_HYPERTHREADING select C_ENVIRONMENT_BOOTBLOCK select FSP_M_XIP if MAINBOARD_USES_FSP2_0 select FSP_T_XIP if FSP_CAR diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 1f9ecad..63142b9 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -420,6 +420,25 @@ wrmsr(MSR_EMULATE_PM_TIMER, msr); }

+/* + * Lock AES-NI (MSR_FEATURE_CONFIG) to prevent unintended disabling + * as suggested in Intel document 325384-070US. + */ +static void cpu_lock_aesni(void) +{ + msr_t msr; + + /* Only run once per core as specified in the MSR datasheet */ + if (intel_ht_sibling()) + return; + + msr = rdmsr(MSR_FEATURE_CONFIG); + if ((msr.lo & 1) == 0) { + msr.lo |= 1; + wrmsr(MSR_FEATURE_CONFIG, msr); + } +} + /* All CPUs including BSP will run the following function. */ void soc_core_init(struct device *cpu) { @@ -444,6 +463,9 @@ /* Configure Intel Speed Shift */ configure_isst();

+ /* Lock AES-NI MSR */ + cpu_lock_aesni(); + /* Enable ACPI Timer Emulation via MSR 0x121 */ enable_pm_timer_emulation();

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participants (9)

Angel Pons (Code Review)
build bot (Jenkins) (Code Review)
Furquan Shaikh (Code Review)
Michael Niewöhner (Code Review)
Nico Huber (Code Review)
Patrick Georgi (Code Review)
Patrick Rudolph (Code Review)
Paul Menzel (Code Review)
Subrata Banik (Code Review)