Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48220 )
Change subject: soc/amd: move smi_util to common block ......................................................................
soc/amd: move smi_util to common block
Since both SoCs unconditionally select HAVE_SMI_HANDLER in their Kconfig and smi_util doesn't use any functions that are only present when this option is selected, so this patch also drops the guards in the Makefile.inc file.
Change-Id: I2f930287840bf7aa958f19786c7f1146c683c93e Signed-off-by: Felix Held felix-coreboot@felixheld.de --- A src/soc/amd/common/block/smi/Kconfig A src/soc/amd/common/block/smi/Makefile.inc R src/soc/amd/common/block/smi/smi_util.c M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/Makefile.inc M src/soc/amd/stoneyridge/Kconfig M src/soc/amd/stoneyridge/Makefile.inc D src/soc/amd/stoneyridge/smi_util.c 8 files changed, 17 insertions(+), 137 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/48220/1
diff --git a/src/soc/amd/common/block/smi/Kconfig b/src/soc/amd/common/block/smi/Kconfig new file mode 100644 index 0000000..1b05b14 --- /dev/null +++ b/src/soc/amd/common/block/smi/Kconfig @@ -0,0 +1,6 @@ +config SOC_AMD_COMMON_BLOCK_SMI + bool + default n + help + Select this option to add the common functions for setting up the SMI + configuration to the build. diff --git a/src/soc/amd/common/block/smi/Makefile.inc b/src/soc/amd/common/block/smi/Makefile.inc new file mode 100644 index 0000000..b6239ae --- /dev/null +++ b/src/soc/amd/common/block/smi/Makefile.inc @@ -0,0 +1,8 @@ +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_SMI),y) + +bootblock-y += smi_util.c +romstage-y += smi_util.c +ramstage-y += smi_util.c +smm-y += smi_util.c + +endif # CONFIG_SOC_AMD_COMMON_BLOCK_SMI diff --git a/src/soc/amd/picasso/smi_util.c b/src/soc/amd/common/block/smi/smi_util.c similarity index 97% rename from src/soc/amd/picasso/smi_util.c rename to src/soc/amd/common/block/smi/smi_util.c index 39b2b95..d63f585 100644 --- a/src/soc/amd/picasso/smi_util.c +++ b/src/soc/amd/common/block/smi/smi_util.c @@ -1,8 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */
-/* - * SMM utilities used in both SMM and normal mode - */ +/* SMI utilities used in both SMM and normal mode */
#include <console/console.h> #include <cpu/x86/smm.h> diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 9e9c99a..5da4731 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -42,6 +42,7 @@ select SOC_AMD_COMMON_BLOCK_HDA select SOC_AMD_COMMON_BLOCK_SATA select SOC_AMD_COMMON_BLOCK_SMBUS + select SOC_AMD_COMMON_BLOCK_SMI select SOC_AMD_COMMON_BLOCK_SMU select SOC_AMD_COMMON_BLOCK_PSP_GEN2 select PROVIDES_ROM_SHARING diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index b5e409b..c772783 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -20,7 +20,6 @@ bootblock-y += monotonic_timer.c bootblock-y += tsc_freq.c bootblock-y += gpio.c -bootblock-y += smi_util.c bootblock-y += config.c bootblock-y += reset.c
@@ -35,7 +34,6 @@ romstage-y += tsc_freq.c romstage-y += aoac.c romstage-y += southbridge.c -romstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c romstage-y += psp.c romstage-y += config.c romstage-y += mrc_cache.c @@ -66,7 +64,6 @@ ramstage-y += sata.c ramstage-y += memmap.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c -ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c ramstage-y += uart.c ramstage-$(CONFIG_PICASSO_CONSOLE_UART) += uart_console.c ramstage-y += monotonic_timer.c @@ -83,7 +80,6 @@ ramstage-y += dmi.c
smm-y += smihandler.c -smm-y += smi_util.c smm-y += monotonic_timer.c smm-y += tsc_freq.c ifeq ($(CONFIG_DEBUG_SMI),y) diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index f24d202..d672726 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -37,6 +37,7 @@ select SOC_AMD_COMMON_BLOCK_CAR select SOC_AMD_COMMON_BLOCK_S3 select SOC_AMD_COMMON_BLOCK_SMBUS + select SOC_AMD_COMMON_BLOCK_SMI select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH select PARALLEL_MP select PARALLEL_MP_AP_WORK diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index 8cdf6cc..969f512 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -19,7 +19,6 @@ bootblock-y += monotonic_timer.c bootblock-y += tsc_freq.c bootblock-y += southbridge.c -bootblock-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c
romstage-y += BiosCallOuts.c romstage-y += i2c.c @@ -32,7 +31,6 @@ romstage-$(CONFIG_STONEYRIDGE_UART) += uart.c romstage-y += tsc_freq.c romstage-y += southbridge.c -romstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c romstage-y += psp.c
verstage-y += gpio.c @@ -61,7 +59,6 @@ ramstage-y += sata.c ramstage-y += memmap.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c -ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c ramstage-$(CONFIG_STONEYRIDGE_UART) += uart.c ramstage-y += usb.c ramstage-y += tsc_freq.c @@ -72,7 +69,6 @@
smm-y += monotonic_timer.c smm-y += smihandler.c -smm-y += smi_util.c smm-y += tsc_freq.c smm-$(CONFIG_DEBUG_SMI) += uart.c smm-y += gpio.c diff --git a/src/soc/amd/stoneyridge/smi_util.c b/src/soc/amd/stoneyridge/smi_util.c deleted file mode 100644 index 39b2b95..0000000 --- a/src/soc/amd/stoneyridge/smi_util.c +++ /dev/null @@ -1,126 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -/* - * SMM utilities used in both SMM and normal mode - */ - -#include <console/console.h> -#include <cpu/x86/smm.h> -#include <soc/southbridge.h> -#include <soc/smi.h> -#include <amdblocks/acpimmio.h> -#include <amdblocks/smi.h> - -void configure_smi(uint8_t smi_num, uint8_t mode) -{ - uint8_t reg32_offset, bit_offset; - uint32_t reg32; - - if (smi_num >= NUMBER_SMITYPES) { - printk(BIOS_WARNING, "BUG: Invalid SMI: %u\n", smi_num); - return; - } - - /* 16 sources per register, 2 bits per source; registers are 4 bytes */ - reg32_offset = (smi_num / 16) * 4; - bit_offset = (smi_num % 16) * 2; - - reg32 = smi_read32(SMI_REG_CONTROL0 + reg32_offset); - reg32 &= ~(0x3 << (bit_offset)); - reg32 |= (mode & 0x3) << bit_offset; - smi_write32(SMI_REG_CONTROL0 + reg32_offset, reg32); -} - -/** - * Configure generation of interrupts for given GEVENT pin - * - * @param gevent The GEVENT pin number. Valid values are 0 thru 23 - * @param mode The type of event this pin should generate. Note that only - * SMI_MODE_SMI generates an SMI. SMI_MODE_DISABLE disables events. - * @param level SMI__SCI_LVL_LOW or SMI_SCI_LVL_HIGH - */ -void configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level) -{ - uint32_t reg32; - /* GEVENT pins range from [0:23] */ - if (gevent >= SMI_GEVENTS) { - printk(BIOS_WARNING, "BUG: Invalid GEVENT: %u\n", gevent); - return; - } - - /* SMI0 source is GEVENT0 and so on */ - configure_smi(gevent, mode); - - /* And set set the trigger level */ - reg32 = smi_read32(SMI_REG_SMITRIG0); - reg32 &= ~(1 << gevent); - reg32 |= (level & 0x1) << gevent; - smi_write32(SMI_REG_SMITRIG0, reg32); -} - -/** - * Configure generation of SCIs. - */ -void configure_scimap(const struct sci_source *sci) -{ - uint32_t reg32; - - /* GEVENT pins range */ - if (sci->scimap >= SCIMAPS) { - printk(BIOS_WARNING, "BUG: Invalid SCIMAP: %u\n", - sci->scimap); - return; - } - - /* GPEs range from [0:31] */ - if (sci->gpe >= SCI_GPES) { - printk(BIOS_WARNING, "BUG: Invalid SCI GPE: %u\n", sci->gpe); - return; - } - - printk(BIOS_DEBUG, "SCIMAP %u maps to GPE %u (active %s, %s trigger)\n", - sci->scimap, sci->gpe, - (!!sci->direction) ? "high" : "low", - (!!sci->level) ? "level" : "edge"); - - /* Map Gevent to SCI GPE# */ - smi_write8(SMI_SCI_MAP(sci->scimap), sci->gpe); - - /* Set the trigger direction (high/low) */ - reg32 = smi_read32(SMI_SCI_TRIG); - reg32 &= ~(1 << sci->gpe); - reg32 |= !!sci->direction << sci->gpe; - smi_write32(SMI_SCI_TRIG, reg32); - - /* Set the trigger level (edge/level) */ - reg32 = smi_read32(SMI_SCI_LEVEL); - reg32 &= ~(1 << sci->gpe); - reg32 |= !!sci->level << sci->gpe; - smi_write32(SMI_SCI_LEVEL, reg32); -} - -void gpe_configure_sci(const struct sci_source *scis, size_t num_gpes) -{ - size_t i; - - for (i = 0; i < num_gpes; i++) - configure_scimap(scis + i); -} - -/** Disable events from given GEVENT pin */ -void disable_gevent_smi(uint8_t gevent) -{ - /* GEVENT pins range from [0:23] */ - if (gevent > 23) { - printk(BIOS_WARNING, "BUG: Invalid GEVENT: %u\n", gevent); - return; - } - - /* SMI0 source is GEVENT0 and so on */ - configure_smi(gevent, SMI_MODE_DISABLE); -} - -uint16_t pm_acpi_smi_cmd_port(void) -{ - return pm_read16(PM_ACPI_SMI_CMD); -}
Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48220 )
Change subject: soc/amd: move smi_util to common block ......................................................................
Patch Set 1:
(1 comment)
How much did you compare these registers/functions with the upcoming devices? IIRC I was reluctant to move SMI stuff to common because there were a number of differences between ST and PCO. I _think_ we're OK with what you have here... Using addresses like SMI_REG_CONTROL0 may eventually need to change (and I'm not sure what Server devices look like, Promontory, etc.), but we can address that later if necessary.
https://review.coreboot.org/c/coreboot/+/48220/1/src/soc/amd/common/block/sm... File src/soc/amd/common/block/smi/smi_util.c:
https://review.coreboot.org/c/coreboot/+/48220/1/src/soc/amd/common/block/sm... PS1, Line 35: Valid values are 0 thru 23 I can't recall, without digging, if this is typically consistent across devices.
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48220 )
Change subject: soc/amd: move smi_util to common block ......................................................................
Patch Set 1:
smi_util.c from picasso was a 1:1 copy of the stoneyridge code
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48220 )
Change subject: soc/amd: move smi_util to common block ......................................................................
Patch Set 1:
Patch Set 1:
smi_util.c from picasso was a 1:1 copy of the stoneyridge code
the mapping of things to the sci number is different in the socs, but i kept that part in the soc/smi.h headers. if you think that i should verify the code also applies to the next generation, i can have a look at it again tomorrow
Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48220 )
Change subject: soc/amd: move smi_util to common block ......................................................................
Patch Set 1:
(2 comments)
Patch Set 1:
Patch Set 1:
smi_util.c from picasso was a 1:1 copy of the stoneyridge code
the mapping of things to the sci number is different in the socs, but i kept that part in the soc/smi.h headers. if you think that i should verify the code also applies to the next generation, i can have a look at it again tomorrow
We need to check the specs anyway, so since it's moving to common it's probably a good time to do it. I think we'll be OK but I want to make sure we use the right amount of caution.
https://review.coreboot.org/c/coreboot/+/48220/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/48220/1//COMMIT_MSG@10 PS1, Line 10: doesn't use any functions that are only present when this : option is selected Maybe reword to end one sentence, stating what you're doing.
https://review.coreboot.org/c/coreboot/+/48220/1//COMMIT_MSG@11 PS1, Line 11: so this patch also drops the guards in the : Makefile.inc file. I'd make this a separate sentence, and not beginning with "so".
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48220 )
Change subject: soc/amd: move smi_util to common block ......................................................................
Patch Set 1:
We need to check the specs anyway, so since it's moving to common it's probably a good time to do it. I think we'll be OK but I want to make sure we use the right amount of caution.
Yeah, i'll verify it tomorrow; only had a brief look at it today, but didn't spot any difference that would affect the code that gets moved to common
Hello build bot (Jenkins), Jason Glenesk, Patrick Georgi, Martin Roth, Marshall Dawson,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48220
to look at the new patch set (#2).
Change subject: soc/amd: move smi_util to common block ......................................................................
soc/amd: move smi_util to common block
The functionality in smi_util applies for all 3 AMD SoCs in tree. This patch additionally drops the HAVE_SMI_HANDLER guards in the common block's Makefile.inc, since all 3 SoCs unconditionally select HAVE_SMI_HANDLER in their Kconfig and smi_util doesn't use any functionality that is only present when that option is selected.
Change-Id: I2f930287840bf7aa958f19786c7f1146c683c93e Signed-off-by: Felix Held felix-coreboot@felixheld.de --- A src/soc/amd/common/block/smi/Kconfig A src/soc/amd/common/block/smi/Makefile.inc R src/soc/amd/common/block/smi/smi_util.c M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/Makefile.inc M src/soc/amd/stoneyridge/Kconfig M src/soc/amd/stoneyridge/Makefile.inc D src/soc/amd/stoneyridge/smi_util.c 8 files changed, 17 insertions(+), 137 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/48220/2
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48220 )
Change subject: soc/amd: move smi_util to common block ......................................................................
Patch Set 2:
(3 comments)
I've verified that this functionality applies to all Stoneyridge, Picasso and Cezanne. Cezanne has a few additional registers. There are also some differences in the smitype numbers, but i kept those in the soc-specific header files in the other related patch that's already merged
https://review.coreboot.org/c/coreboot/+/48220/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/48220/1//COMMIT_MSG@10 PS1, Line 10: doesn't use any functions that are only present when this : option is selected
Maybe reword to end one sentence, stating what you're doing.
Done
https://review.coreboot.org/c/coreboot/+/48220/1//COMMIT_MSG@11 PS1, Line 11: so this patch also drops the guards in the : Makefile.inc file.
I'd make this a separate sentence, and not beginning with "so".
Done
https://review.coreboot.org/c/coreboot/+/48220/1/src/soc/amd/common/block/sm... File src/soc/amd/common/block/smi/smi_util.c:
https://review.coreboot.org/c/coreboot/+/48220/1/src/soc/amd/common/block/sm... PS1, Line 35: Valid values are 0 thru 23
I can't recall, without digging, if this is typically consistent across devices.
just checked and it's at least consistent between stoneyridge, picasso and cezanne
Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48220 )
Change subject: soc/amd: move smi_util to common block ......................................................................
Patch Set 2: Code-Review+2
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48220 )
Change subject: soc/amd: move smi_util to common block ......................................................................
soc/amd: move smi_util to common block
The functionality in smi_util applies for all 3 AMD SoCs in tree. This patch additionally drops the HAVE_SMI_HANDLER guards in the common block's Makefile.inc, since all 3 SoCs unconditionally select HAVE_SMI_HANDLER in their Kconfig and smi_util doesn't use any functionality that is only present when that option is selected.
Change-Id: I2f930287840bf7aa958f19786c7f1146c683c93e Signed-off-by: Felix Held felix-coreboot@felixheld.de Reviewed-on: https://review.coreboot.org/c/coreboot/+/48220 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Marshall Dawson marshalldawson3rd@gmail.com --- A src/soc/amd/common/block/smi/Kconfig A src/soc/amd/common/block/smi/Makefile.inc R src/soc/amd/common/block/smi/smi_util.c M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/Makefile.inc M src/soc/amd/stoneyridge/Kconfig M src/soc/amd/stoneyridge/Makefile.inc D src/soc/amd/stoneyridge/smi_util.c 8 files changed, 17 insertions(+), 137 deletions(-)
Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved
diff --git a/src/soc/amd/common/block/smi/Kconfig b/src/soc/amd/common/block/smi/Kconfig new file mode 100644 index 0000000..1b05b14 --- /dev/null +++ b/src/soc/amd/common/block/smi/Kconfig @@ -0,0 +1,6 @@ +config SOC_AMD_COMMON_BLOCK_SMI + bool + default n + help + Select this option to add the common functions for setting up the SMI + configuration to the build. diff --git a/src/soc/amd/common/block/smi/Makefile.inc b/src/soc/amd/common/block/smi/Makefile.inc new file mode 100644 index 0000000..b6239ae --- /dev/null +++ b/src/soc/amd/common/block/smi/Makefile.inc @@ -0,0 +1,8 @@ +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_SMI),y) + +bootblock-y += smi_util.c +romstage-y += smi_util.c +ramstage-y += smi_util.c +smm-y += smi_util.c + +endif # CONFIG_SOC_AMD_COMMON_BLOCK_SMI diff --git a/src/soc/amd/picasso/smi_util.c b/src/soc/amd/common/block/smi/smi_util.c similarity index 97% rename from src/soc/amd/picasso/smi_util.c rename to src/soc/amd/common/block/smi/smi_util.c index 39b2b95..d63f585 100644 --- a/src/soc/amd/picasso/smi_util.c +++ b/src/soc/amd/common/block/smi/smi_util.c @@ -1,8 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */
-/* - * SMM utilities used in both SMM and normal mode - */ +/* SMI utilities used in both SMM and normal mode */
#include <console/console.h> #include <cpu/x86/smm.h> diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index e2feebd..2ac1235 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -42,6 +42,7 @@ select SOC_AMD_COMMON_BLOCK_HDA select SOC_AMD_COMMON_BLOCK_SATA select SOC_AMD_COMMON_BLOCK_SMBUS + select SOC_AMD_COMMON_BLOCK_SMI select SOC_AMD_COMMON_BLOCK_SMU select SOC_AMD_COMMON_BLOCK_PSP_GEN2 select PROVIDES_ROM_SHARING diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index b5e409b..c772783 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -20,7 +20,6 @@ bootblock-y += monotonic_timer.c bootblock-y += tsc_freq.c bootblock-y += gpio.c -bootblock-y += smi_util.c bootblock-y += config.c bootblock-y += reset.c
@@ -35,7 +34,6 @@ romstage-y += tsc_freq.c romstage-y += aoac.c romstage-y += southbridge.c -romstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c romstage-y += psp.c romstage-y += config.c romstage-y += mrc_cache.c @@ -66,7 +64,6 @@ ramstage-y += sata.c ramstage-y += memmap.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c -ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c ramstage-y += uart.c ramstage-$(CONFIG_PICASSO_CONSOLE_UART) += uart_console.c ramstage-y += monotonic_timer.c @@ -83,7 +80,6 @@ ramstage-y += dmi.c
smm-y += smihandler.c -smm-y += smi_util.c smm-y += monotonic_timer.c smm-y += tsc_freq.c ifeq ($(CONFIG_DEBUG_SMI),y) diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index f24d202..d672726 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -37,6 +37,7 @@ select SOC_AMD_COMMON_BLOCK_CAR select SOC_AMD_COMMON_BLOCK_S3 select SOC_AMD_COMMON_BLOCK_SMBUS + select SOC_AMD_COMMON_BLOCK_SMI select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH select PARALLEL_MP select PARALLEL_MP_AP_WORK diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index 8cdf6cc..969f512 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -19,7 +19,6 @@ bootblock-y += monotonic_timer.c bootblock-y += tsc_freq.c bootblock-y += southbridge.c -bootblock-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c
romstage-y += BiosCallOuts.c romstage-y += i2c.c @@ -32,7 +31,6 @@ romstage-$(CONFIG_STONEYRIDGE_UART) += uart.c romstage-y += tsc_freq.c romstage-y += southbridge.c -romstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c romstage-y += psp.c
verstage-y += gpio.c @@ -61,7 +59,6 @@ ramstage-y += sata.c ramstage-y += memmap.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c -ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c ramstage-$(CONFIG_STONEYRIDGE_UART) += uart.c ramstage-y += usb.c ramstage-y += tsc_freq.c @@ -72,7 +69,6 @@
smm-y += monotonic_timer.c smm-y += smihandler.c -smm-y += smi_util.c smm-y += tsc_freq.c smm-$(CONFIG_DEBUG_SMI) += uart.c smm-y += gpio.c diff --git a/src/soc/amd/stoneyridge/smi_util.c b/src/soc/amd/stoneyridge/smi_util.c deleted file mode 100644 index 39b2b95..0000000 --- a/src/soc/amd/stoneyridge/smi_util.c +++ /dev/null @@ -1,126 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -/* - * SMM utilities used in both SMM and normal mode - */ - -#include <console/console.h> -#include <cpu/x86/smm.h> -#include <soc/southbridge.h> -#include <soc/smi.h> -#include <amdblocks/acpimmio.h> -#include <amdblocks/smi.h> - -void configure_smi(uint8_t smi_num, uint8_t mode) -{ - uint8_t reg32_offset, bit_offset; - uint32_t reg32; - - if (smi_num >= NUMBER_SMITYPES) { - printk(BIOS_WARNING, "BUG: Invalid SMI: %u\n", smi_num); - return; - } - - /* 16 sources per register, 2 bits per source; registers are 4 bytes */ - reg32_offset = (smi_num / 16) * 4; - bit_offset = (smi_num % 16) * 2; - - reg32 = smi_read32(SMI_REG_CONTROL0 + reg32_offset); - reg32 &= ~(0x3 << (bit_offset)); - reg32 |= (mode & 0x3) << bit_offset; - smi_write32(SMI_REG_CONTROL0 + reg32_offset, reg32); -} - -/** - * Configure generation of interrupts for given GEVENT pin - * - * @param gevent The GEVENT pin number. Valid values are 0 thru 23 - * @param mode The type of event this pin should generate. Note that only - * SMI_MODE_SMI generates an SMI. SMI_MODE_DISABLE disables events. - * @param level SMI__SCI_LVL_LOW or SMI_SCI_LVL_HIGH - */ -void configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level) -{ - uint32_t reg32; - /* GEVENT pins range from [0:23] */ - if (gevent >= SMI_GEVENTS) { - printk(BIOS_WARNING, "BUG: Invalid GEVENT: %u\n", gevent); - return; - } - - /* SMI0 source is GEVENT0 and so on */ - configure_smi(gevent, mode); - - /* And set set the trigger level */ - reg32 = smi_read32(SMI_REG_SMITRIG0); - reg32 &= ~(1 << gevent); - reg32 |= (level & 0x1) << gevent; - smi_write32(SMI_REG_SMITRIG0, reg32); -} - -/** - * Configure generation of SCIs. - */ -void configure_scimap(const struct sci_source *sci) -{ - uint32_t reg32; - - /* GEVENT pins range */ - if (sci->scimap >= SCIMAPS) { - printk(BIOS_WARNING, "BUG: Invalid SCIMAP: %u\n", - sci->scimap); - return; - } - - /* GPEs range from [0:31] */ - if (sci->gpe >= SCI_GPES) { - printk(BIOS_WARNING, "BUG: Invalid SCI GPE: %u\n", sci->gpe); - return; - } - - printk(BIOS_DEBUG, "SCIMAP %u maps to GPE %u (active %s, %s trigger)\n", - sci->scimap, sci->gpe, - (!!sci->direction) ? "high" : "low", - (!!sci->level) ? "level" : "edge"); - - /* Map Gevent to SCI GPE# */ - smi_write8(SMI_SCI_MAP(sci->scimap), sci->gpe); - - /* Set the trigger direction (high/low) */ - reg32 = smi_read32(SMI_SCI_TRIG); - reg32 &= ~(1 << sci->gpe); - reg32 |= !!sci->direction << sci->gpe; - smi_write32(SMI_SCI_TRIG, reg32); - - /* Set the trigger level (edge/level) */ - reg32 = smi_read32(SMI_SCI_LEVEL); - reg32 &= ~(1 << sci->gpe); - reg32 |= !!sci->level << sci->gpe; - smi_write32(SMI_SCI_LEVEL, reg32); -} - -void gpe_configure_sci(const struct sci_source *scis, size_t num_gpes) -{ - size_t i; - - for (i = 0; i < num_gpes; i++) - configure_scimap(scis + i); -} - -/** Disable events from given GEVENT pin */ -void disable_gevent_smi(uint8_t gevent) -{ - /* GEVENT pins range from [0:23] */ - if (gevent > 23) { - printk(BIOS_WARNING, "BUG: Invalid GEVENT: %u\n", gevent); - return; - } - - /* SMI0 source is GEVENT0 and so on */ - configure_smi(gevent, SMI_MODE_DISABLE); -} - -uint16_t pm_acpi_smi_cmd_port(void) -{ - return pm_read16(PM_ACPI_SMI_CMD); -}
-
Felix Held (Code Review) -
Marshall Dawson (Code Review)