Attention is currently required from: Hung-Te Lin, Yu-Ping Wu.
Yidi Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84114?usp=email )
Change subject: soc/mediatek/common/pcie: Use clr/setbits32p ......................................................................
soc/mediatek/common/pcie: Use clr/setbits32p
Use clr/setbits32p to make code cleaner.
BUG=none TEST=emerge-cherry coreboot
Change-Id: Id99d5aafdf4d687dbe3a0bef29b148537cf58dd8 Signed-off-by: Yidi Lin yidilin@chromium.org --- M src/soc/mediatek/common/pcie.c 1 file changed, 4 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/84114/1
diff --git a/src/soc/mediatek/common/pcie.c b/src/soc/mediatek/common/pcie.c index c07cc4f..39714e1 100644 --- a/src/soc/mediatek/common/pcie.c +++ b/src/soc/mediatek/common/pcie.c @@ -266,20 +266,14 @@ uint32_t val;
/* Set as RC mode */ - val = read32p(conf->base + PCIE_SETTING_REG); - val |= PCIE_RC_MODE; - write32p(conf->base + PCIE_SETTING_REG, val); + setbits32p(conf->base + PCIE_SETTING_REG, PCIE_RC_MODE);
/* Set class code */ - val = read32p(conf->base + PCIE_PCI_IDS_1); - val &= ~GENMASK(31, 8); - val |= PCI_CLASS(PCI_CLASS_BRIDGE_PCI << 8); - write32p(conf->base + PCIE_PCI_IDS_1, val); + clrsetbits32p(conf->base + PCIE_PCI_IDS_1, GENMASK(31, 8), + PCI_CLASS(PCI_CLASS_BRIDGE_PCI << 8));
/* Mask all INTx interrupts */ - val = read32p(conf->base + PCIE_INT_ENABLE_REG); - val &= ~PCIE_INTX_ENABLE; - write32p(conf->base + PCIE_INT_ENABLE_REG, val); + clrbits32p(conf->base + PCIE_INT_ENABLE_REG, PCIE_INTX_ENABLE);
perst_time_us = early_init_get_elapsed_time_us(EARLY_INIT_PCIE); printk(BIOS_DEBUG, "%s: %ld us elapsed since assert PERST#\n",