Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29969 )
Change subject: qcs405: memlayout: Make bootblock 64k aligned ......................................................................
Patch Set 13:
(5 comments)
https://review.coreboot.org/#/c/29969/13//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/29969/13//COMMIT_MSG@9 PS13, Line 9: excepts that expects
https://review.coreboot.org/#/c/29969/13/src/arch/arm64/armv8/bootblock.S File src/arch/arm64/armv8/bootblock.S:
https://review.coreboot.org/#/c/29969/13/src/arch/arm64/armv8/bootblock.S@26 PS13, Line 26: ldr x15, =arm64_init_cpu while this change shouldn't hurt, it's also not explained by the commit message. what is it for?
https://review.coreboot.org/#/c/29969/13/src/soc/qualcomm/qcs405/include/soc... File src/soc/qualcomm/qcs405/include/soc/memlayout.ld:
https://review.coreboot.org/#/c/29969/13/src/soc/qualcomm/qcs405/include/soc... PS13, Line 35: BOOTBLOCK(0x8C30000, 40K) maybe add an _bogus = ASSERT(bootblock & 0xffff == 0, "bootblock must be 64K aligned"); somewhere?
https://review.coreboot.org/#/c/29969/13/src/soc/qualcomm/qcs405/include/soc... PS13, Line 36: x8C3a coreboot prefers hex values in lower case, but whatever you do, please don't mix them :-)
https://review.coreboot.org/#/c/29969/13/src/soc/qualcomm/qcs405/include/soc... PS13, Line 44: //REGION(dcb, 0x8CEa000, 0x4000, 4096) that change is unexplained
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Patrick Georgi (Code Review)