Attention is currently required from: Benjamin Doron, Dinesh Gehlot, Kapil Porwal, Nick Vaccaro, Subrata Banik.
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81936?usp=email )
Change subject: soc/intel/alderlake: Refactor CrashLog BAR helpers
......................................................................
Patch Set 1:
(1 comment)
File src/soc/intel/alderlake/crashlog.c:
https://review.coreboot.org/c/coreboot/+/81936/comment/34ace578_c5591ff6 :
PS1, Line 43: pci_read_config32(SA_DEV_TMT, PCI_BASE_ADDRESS_0) &
: ~PCI_BASE_ADDRESS_MEM_ATTR_MASK;
is the bar MEM32 ? Otherwise you need the upper 32bit too.
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