Change in coreboot[master]: soc/amd/picasso/southbridge.h: remove OSCOUT*_CLK_OUTPUT_ENB definitions
Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44886 )
Change subject: soc/amd/picasso/southbridge.h: remove OSCOUT*_CLK_OUTPUT_ENB definitions ......................................................................
soc/amd/picasso/southbridge.h: remove OSCOUT*_CLK_OUTPUT_ENB definitions
On Picasso MISC_CLK_CNTL1 doesn't contain OSCOUT[12]_CLK_OUTPUT_ENB and this was probably just copied over from stoneyridge.
BUG=b:149970243 BRANCH=zork
Change-Id: I32f459026c4e8632672123681b20736245f198b2 Signed-off-by: Felix Held felix-coreboot@felixheld.de --- M src/soc/amd/picasso/include/soc/southbridge.h 1 file changed, 0 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/44886/1
diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index e4ae8dc..033bcbf 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -161,8 +161,6 @@ #define CG1PLL_SPREAD_SPECTRUM_ENABLE BIT(0) #define MISC_CLK_CNTL1 0x40 #define BP_X48M0_OUTPUT_EN BIT(2) /* 1=En, unlike Hudson, Kern */ -#define OSCOUT1_CLK_OUTPUT_ENB BIT(2) /* 0 = Enabled, 1 = Disabled */ -#define OSCOUT2_CLK_OUTPUT_ENB BIT(7) /* 0 = Enabled, 1 = Disabled */ #define MISC_I2C0_PAD_CTRL 0xd8 #define MISC_I2C1_PAD_CTRL 0xdc #define MISC_I2C2_PAD_CTRL 0xe0
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44886 )
Change subject: soc/amd/picasso/southbridge.h: remove OSCOUT*_CLK_OUTPUT_ENB definitions ......................................................................
Patch Set 1: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44886 )
Change subject: soc/amd/picasso/southbridge.h: remove OSCOUT*_CLK_OUTPUT_ENB definitions ......................................................................
soc/amd/picasso/southbridge.h: remove OSCOUT*_CLK_OUTPUT_ENB definitions
On Picasso MISC_CLK_CNTL1 doesn't contain OSCOUT[12]_CLK_OUTPUT_ENB and this was probably just copied over from stoneyridge.
BUG=b:149970243 BRANCH=zork
Change-Id: I32f459026c4e8632672123681b20736245f198b2 Signed-off-by: Felix Held felix-coreboot@felixheld.de Reviewed-on: https://review.coreboot.org/c/coreboot/+/44886 Reviewed-by: Aaron Durbin adurbin@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/amd/picasso/include/soc/southbridge.h 1 file changed, 0 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Aaron Durbin: Looks good to me, approved
diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index e4ae8dc..033bcbf 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -161,8 +161,6 @@ #define CG1PLL_SPREAD_SPECTRUM_ENABLE BIT(0) #define MISC_CLK_CNTL1 0x40 #define BP_X48M0_OUTPUT_EN BIT(2) /* 1=En, unlike Hudson, Kern */ -#define OSCOUT1_CLK_OUTPUT_ENB BIT(2) /* 0 = Enabled, 1 = Disabled */ -#define OSCOUT2_CLK_OUTPUT_ENB BIT(7) /* 0 = Enabled, 1 = Disabled */ #define MISC_I2C0_PAD_CTRL 0xd8 #define MISC_I2C1_PAD_CTRL 0xdc #define MISC_I2C2_PAD_CTRL 0xe0
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44886 )
Change subject: soc/amd/picasso/southbridge.h: remove OSCOUT*_CLK_OUTPUT_ENB definitions ......................................................................
Patch Set 2:
Automatic boot test returned (PASS/FAIL/TOTAL): 6/1/7 "QEMU x86 q35/ich9" (x86_32) using payload TianoCore : SUCCESS : https://lava.9esec.io/r/17293 "QEMU x86 q35/ich9" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/17292 "QEMU x86 i440fx/piix4" (x86_64) using payload SeaBIOS : FAIL : https://lava.9esec.io/r/17291 "QEMU x86 i440fx/piix4" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/17290 "QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/17289 "HP Compaq 8200 Elite SFF PC" (x86_32) using payload TianoCore : SUCCESS : https://lava.9esec.io/r/17295 "HP Compaq 8200 Elite SFF PC" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/17294
Please note: This test is under development and might not be accurate at all!
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9elements QA (Code Review) -
Aaron Durbin (Code Review)
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Felix Held (Code Review)
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Patrick Georgi (Code Review)