Attention is currently required from: Chen, Gang C, David Hendricks, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Paul Menzel, Shuo Liu, TangYiwei.
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81322?usp=email )
Change subject: mb/intel/beechnutcity_crb: Add GNR/SRF-SP 2S server board Beechnut City ......................................................................
Patch Set 11: Code-Review+2
(4 comments)
Patchset:
PS11: Looks good. A few nits
File configs/builder/config.intel.crb.bnc:
https://review.coreboot.org/c/coreboot/+/81322/comment/9dab4f8e_54d5b5a4 : PS11, Line 27: # : CONFIG_IFD_BIN_PATH="site-local/beechnutcity/descriptor.bin" : CONFIG_CPU_UCODE_BINARIES="site-local/beechnutcity/ucode.mcb" : CONFIG_FSP_T_FILE="site-local/beechnutcity/Server_T.fd" : CONFIG_FSP_M_FILE="site-local/beechnutcity/Server_M.fd" : CONFIG_FSP_S_FILE="site-local/beechnutcity/Server_S.fd" : CONFIG_FSP_HEADER_PATH="src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/" I'm not sure if upstream code should have references to site-local stuff?
File src/mainboard/intel/beechnutcity_crb/Kconfig:
https://review.coreboot.org/c/coreboot/+/81322/comment/a3e14dc4_41ff0265 : PS11, Line 8: select MAINBOARD_USES_FSP2_0 This should be removed (also from all other xeon_sp boards)
File src/mainboard/intel/beechnutcity_crb/romstage.c:
https://review.coreboot.org/c/coreboot/+/81322/comment/760c7179_78b94bd8 : PS11, Line 21: /* Set BIOS regeion UPD, otherwise MTRR might set incorrectly during TempRamExit API */ : mupd->FspmConfig.BiosRegionBase = FMAP_SECTION_SI_ALL_START + FMAP_SECTION_SI_ALL_SIZE; : mupd->FspmConfig.BiosRegionSize = FMAP_SECTION_FLASH_SIZE - FMAP_SECTION_SI_ALL_SIZE; This is not mainboard specific.
I suggest adding a SI_BIOS region that has all the memory mapped stuff below it and use that instead of doing some computations.