Attention is currently required from: Raul Rangel, Marshall Dawson, Paul Menzel, Matt Papageorge, Felix Held. Hello build bot (Jenkins), Raul Rangel, Marshall Dawson, Paul Menzel, Karthik Ramasubramanian, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/58198
to look at the new patch set (#2).
Change subject: mb/google/guybrush: Add PCIe Reset GPIO69 to SD DXIO Descriptor ......................................................................
mb/google/guybrush: Add PCIe Reset GPIO69 to SD DXIO Descriptor
coreboot normally owns PCIe resets for all Cezanne based systems. However during S0i3 resume coreboot cannot intervene for S0 GPIOs (S5 carry over fine) so we needed an alternate way to de-assert this reset on guybrush. This change feeds in the given S0 reset GPIO (69 in this case) so that SMU may de-assert this reset on S0i3 resume.
BUG=b:199780346 TEST=With latest FSP verify SD device trains each of 10 cycles
Cq-Depend: chrome-internal:4157948 Change-Id: Ieee31651db30147fda84ee1aa31df7cb1c206356 Signed-off-by: Matt Papageorge matthewpapa07@gmail.com --- M src/mainboard/google/guybrush/port_descriptors.c 1 file changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/58198/2