Change in coreboot[master]: soc/intel/common/../cse: Create APIs for CSE read/write operations

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/57804 )

Change subject: soc/intel/common/../cse: Create APIs for CSE read/write operations
......................................................................

soc/intel/common/../cse: Create APIs for CSE read/write operations

This patch ensures CSE read/write APIs are available publically for
other modules/boot stages to consume.

Additionally, create a new API for performing write into CSE PCI device
configuration space aka. me_write_config32().

BUG=b:200644229
TEST=Able to build and boot ADLRVP-P.

Change-Id: Ia480877822d343f2b4c9bf87b246812186d49ea3
Signed-off-by: Subrata Banik 
---
M src/soc/intel/common/block/cse/cse.c
M src/soc/intel/common/block/include/intelblocks/cse.h
2 files changed, 14 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/57804/1

diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c
index 1cea7d9..ccfbc33 100644
--- a/src/soc/intel/common/block/cse/cse.c
+++ b/src/soc/intel/common/block/cse/cse.c
@@ -116,7 +116,7 @@
    return bar & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK;
 }

-static uint32_t read_bar(uint32_t offset)
+uint32_t read_bar(uint32_t offset)
 {
    /* Load and cache BAR */
    if (!cse.sec_bar)
@@ -124,7 +124,7 @@
    return read32((void *)(cse.sec_bar + offset));
 }

-static void write_bar(uint32_t offset, uint32_t val)
+void write_bar(uint32_t offset, uint32_t val)
 {
    /* Load and cache BAR */
    if (!cse.sec_bar)
@@ -612,6 +612,11 @@
    return pci_read_config32(PCH_DEV_CSE, offset);
 }

+void me_write_config32(int offset, uint32_t value)
+{
+	pci_write_config32(PCH_DEV_CSE, offset, value);
+}
+
 static bool cse_is_global_reset_allowed(void)
 {
    /*
diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h
index 9753798..7f43b0f 100644
--- a/src/soc/intel/common/block/include/intelblocks/cse.h
+++ b/src/soc/intel/common/block/include/intelblocks/cse.h
@@ -131,6 +131,10 @@
 /* set up device for use in early boot enviroument with temp bar */
 void heci_init(uintptr_t bar);

+uint32_t read_bar(uint32_t offset);
+
+void write_bar(uint32_t offset, uint32_t val);
+
 /*
  * Send message from BIOS_HOST_ADDR to cse_addr.
  * Sends snd_msg of size snd_sz, and reads message into buffer pointed by
@@ -152,6 +156,9 @@
 /* Reads config value from a specified offset in the CSE PCI Config space. */
 uint32_t me_read_config32(int offset);

+/* Write config value into a specified offset in the CSE PCI Config space. */
+void me_write_config32(int offset, uint32_t value);
+
 /*
  * Check if the CSE device is enabled in device tree. Also check if the device
  * is visible on the PCI bus by reading config space.