Change in coreboot[master]: sb/intel/i82371eb: Consolidate bootblock.c logic

[Keith Hui (Code Review)]

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/21468

Change subject: sb/intel/i82371eb: Consolidate bootblock.c logic
......................................................................

sb/intel/i82371eb: Consolidate bootblock.c logic

The southbridge bootblock entry point bootblock_southbridge_init()
just calls i82371eb_enable_rom() which does all the work. Move all
that code into bootblock_southbridge_init() and drop the second
function.

Plus combine the 3 lines that set 3 bits in XBCS into one.

Change-Id: I07a5a28c91da9586e3bdaaf4521cba3f53a5cc01
Signed-off-by: Keith Hui 
---
M src/southbridge/intel/i82371eb/bootblock.c
1 file changed, 2 insertions(+), 9 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/21468/1

diff --git a/src/southbridge/intel/i82371eb/bootblock.c b/src/southbridge/intel/i82371eb/bootblock.c
index 07f94f3..6f52aa7 100644
--- a/src/southbridge/intel/i82371eb/bootblock.c
+++ b/src/southbridge/intel/i82371eb/bootblock.c
@@ -19,7 +19,7 @@
 #include <device/pci_ids.h>
 #include "i82371eb.h"

-static void i82371eb_enable_rom(void)
+static void bootblock_southbridge_init(void)
 {
    u16 reg16;
    pci_devfn_t dev;
@@ -36,14 +36,7 @@

/* Enable access to the whole ROM, disable ROM write access. */
    reg16 = pci_read_config16(dev, XBCS);
-	reg16 |= LOWER_BIOS_ENABLE;
-	reg16 |= EXT_BIOS_ENABLE;
-	reg16 |= EXT_BIOS_ENABLE_1MB;
+	reg16 |= (LOWER_BIOS_ENABLE | EXT_BIOS_ENABLE | EXT_BIOS_ENABLE_1MB);
    reg16 &= ~(WRITE_PROTECT_ENABLE);	/* Disable ROM write access. */
    pci_write_config16(dev, XBCS, reg16);
-}
-
-static void bootblock_southbridge_init(void)
-{
-	i82371eb_enable_rom();
 }