Change in coreboot[master]: soc/intel: Rename some SMM support functions - coreboot-gerrit

13 Aug 2019

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34856 )
Change subject: soc/intel: Rename some SMM support functions
......................................................................
soc/intel: Rename some SMM support functions
Rename southbridge_smm_X to smm_southbridge_X.
Rename smm_southcluster_X to smm_southbridge_X.
Change-Id: I4f6f9207ba32cf51d75b9ca9230e38310a33a311
Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com
---
M src/cpu/intel/haswell/haswell.h
M src/cpu/intel/haswell/haswell_init.c
M src/cpu/intel/haswell/smmrelocate.c
M src/cpu/intel/smm/gen1/smi.h
M src/cpu/intel/smm/gen1/smmrelocate.c
M src/include/cpu/intel/smm_reloc.h
M src/northbridge/intel/haswell/haswell.h
M src/soc/intel/baytrail/cpu.c
M src/soc/intel/baytrail/include/soc/smm.h
M src/soc/intel/baytrail/smm.c
M src/soc/intel/braswell/cpu.c
M src/soc/intel/braswell/include/soc/smm.h
M src/soc/intel/braswell/smm.c
M src/soc/intel/broadwell/cpu.c
M src/soc/intel/broadwell/include/soc/smm.h
M src/soc/intel/broadwell/smi.c
M src/soc/intel/broadwell/smmrelocate.c
M src/soc/intel/cannonlake/include/soc/smm.h
M src/soc/intel/common/block/include/intelblocks/smm.h
M src/soc/intel/denverton_ns/cpu.c
M src/soc/intel/denverton_ns/include/soc/smm.h
M src/soc/intel/denverton_ns/smm.c
M src/soc/intel/fsp_baytrail/cpu.c
M src/soc/intel/fsp_baytrail/include/soc/smm.h
M src/soc/intel/fsp_baytrail/smm.c
M src/soc/intel/fsp_broadwell_de/cpu.c
M src/soc/intel/fsp_broadwell_de/include/soc/smm.h
M src/soc/intel/fsp_broadwell_de/smi.c
M src/soc/intel/fsp_broadwell_de/smmrelocate.c
M src/soc/intel/icelake/include/soc/smm.h
M src/soc/intel/skylake/include/soc/smm.h
M src/southbridge/intel/common/smi.c
M src/southbridge/intel/lynxpoint/pch.h
M src/southbridge/intel/lynxpoint/smi.c
34 files changed, 73 insertions(+), 303 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/34856/1

diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h
index cfd9d45..d959a23 100644
--- a/src/cpu/intel/haswell/haswell.h
+++ b/src/cpu/intel/haswell/haswell.h
@@ -154,13 +154,6 @@
 /* Configure power limits for turbo mode */
 void set_power_limits(u8 power_limit_1_time);
 int cpu_config_tdp_levels(void);
-void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
-				uintptr_t staggered_smbase);
-void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
-		size_t *smm_save_state_size);
-void smm_initialize(void);
-void smm_relocate(void);
-void smm_lock(void);
 struct bus;
 void bsp_init_and_start_aps(struct bus *cpu_bus);
 /* Determine if HyperThreading is disabled. The variable is not valid until
diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c
index 95d719c..7c2b464 100644
--- a/src/cpu/intel/haswell/haswell_init.c
+++ b/src/cpu/intel/haswell/haswell_init.c
@@ -761,7 +761,7 @@
 {
    /* Now that all APs have been relocated as well as the BSP let SMIs
     * start flowing. */
-	southbridge_smm_enable_smi();
+	smm_southbridge_enable_smi();
/* Lock down the SMRAM space. */
    smm_lock();
diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c
index 6f67709..85b8ba5 100644
--- a/src/cpu/intel/haswell/smmrelocate.c
+++ b/src/cpu/intel/haswell/smmrelocate.c
@@ -260,7 +260,7 @@
 void smm_initialize(void)
 {
    /* Clear the SMM state in the southbridge. */
-	southbridge_smm_clear_state();
+	smm_southbridge_clear_state();
/*
     * Run the relocation handler for on the BSP to check and set up
diff --git a/src/cpu/intel/smm/gen1/smi.h b/src/cpu/intel/smm/gen1/smi.h
index 961a6ec..5204ec3 100644
--- a/src/cpu/intel/smm/gen1/smi.h
+++ b/src/cpu/intel/smm/gen1/smi.h
@@ -22,11 +22,4 @@
 bool cpu_has_alternative_smrr(void);
/* parallel MP helper functions */
-void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
-		size_t *smm_save_state_size);
-void smm_initialize(void);
-void southbridge_smm_clear_state(void);
-void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
-			uintptr_t staggered_smbase);
-void smm_relocate(void);
-void smm_lock(void);
+void smm_southbridge_clear_state(void);
diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c
index 4127d2c..4913977 100644
--- a/src/cpu/intel/smm/gen1/smmrelocate.c
+++ b/src/cpu/intel/smm/gen1/smmrelocate.c
@@ -41,13 +41,6 @@
 #define  G_SMRAME	(1 << 3)
 #define  C_BASE_SEG	((0 << 2) | (1 << 1) | (0 << 0))
-struct ied_header {
-	char signature[10];
-	u32 size;
-	u8 reserved[34];
-} __packed;
-
-
/* On model_6fx, model_1067x and model_106cx SMRR functions slightly
    differently. The MSR are at different location from the rest
@@ -158,7 +151,7 @@
 void smm_initialize(void)
 {
    /* Clear the SMM state in the southbridge. */
-	southbridge_smm_clear_state();
+	smm_southbridge_clear_state();
/*
     * Run the relocation handler for on the BSP to check and set up
diff --git a/src/include/cpu/intel/smm_reloc.h b/src/include/cpu/intel/smm_reloc.h
index e8917ee..d8793ce 100644
--- a/src/include/cpu/intel/smm_reloc.h
+++ b/src/include/cpu/intel/smm_reloc.h
@@ -74,4 +74,16 @@
    wrmsr(MSR_UNCORE_PRMRR_PHYS_MASK, relo_params->uncore_prmrr_mask);
 }
+void smm_lock(void);
+void smm_relocate(void);
+void smm_initialize(void);
+
+/* The initialization of the southbridge is split into 2 components. One is
+ * for clearing the state in the SMM registers. The other is for enabling
+ * SMIs. They are split so that other work between the 2 actions. */
+void smm_southbridge_clear_state(void);
+void smm_southbridge_enable_smi(void);
+void smm_southbridge_enable_smi(void);
+void smm_southcluster_save_gpio_route(uint32_t route);
+
 #endif
diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h
index e02a2a1..55c0b4b 100644
--- a/src/northbridge/intel/haswell/haswell.h
+++ b/src/northbridge/intel/haswell/haswell.h
@@ -208,7 +208,6 @@
 #ifndef __ASSEMBLER__
 static inline void barrier(void) { asm("" ::: "memory"); }
-
 #ifdef __SMM__
 void intel_northbridge_haswell_finalize_smm(void);
 #else /* !__SMM__ */
diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c
index 0f6969c..67b0295 100644
--- a/src/soc/intel/baytrail/cpu.c
+++ b/src/soc/intel/baytrail/cpu.c
@@ -199,10 +199,10 @@
    .get_cpu_count = get_cpu_count,
    .get_smm_info = get_smm_info,
    .get_microcode_info = get_microcode_info,
-	.pre_mp_smm_init = southcluster_smm_clear_state,
+	.pre_mp_smm_init = smm_southbridge_clear_state,
    .per_cpu_smm_trigger = per_cpu_smm_trigger,
    .relocation_handler = relocation_handler,
-	.post_mp_init = southcluster_smm_enable_smi,
+	.post_mp_init = smm_southbridge_enable_smi,
 };
void baytrail_init_cpus(struct device *dev)
diff --git a/src/soc/intel/baytrail/include/soc/smm.h b/src/soc/intel/baytrail/include/soc/smm.h
index f67cd31..8b13789 100644
--- a/src/soc/intel/baytrail/include/soc/smm.h
+++ b/src/soc/intel/baytrail/include/soc/smm.h
@@ -1,32 +1 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#ifndef _BAYTRAIL_SMM_H_
-#define _BAYTRAIL_SMM_H_
-
-#if !defined(__PRE_RAM__) && !defined(__SMM___)
-#include <stdint.h>
-void southcluster_smm_clear_state(void);
-void southcluster_smm_enable_smi(void);
-void southcluster_smm_save_param(int param, uint32_t data);
-#endif
-
-enum {
-	SMM_SAVE_PARAM_GPIO_ROUTE = 0,
-	SMM_SAVE_PARAM_PCIE_WAKE_ENABLE,
-	SMM_SAVE_PARAM_COUNT
-};
-
-#endif /* _BAYTRAIL_SMM_H_ */
diff --git a/src/soc/intel/baytrail/smm.c b/src/soc/intel/baytrail/smm.c
index 42bc518..3f32a08 100644
--- a/src/soc/intel/baytrail/smm.c
+++ b/src/soc/intel/baytrail/smm.c
@@ -24,15 +24,22 @@
 #include <soc/pmc.h>
 #include <soc/smm.h>
+enum {
+	SMM_SAVE_PARAM_GPIO_ROUTE = 0,
+	SMM_SAVE_PARAM_PCIE_WAKE_ENABLE,
+	SMM_SAVE_PARAM_COUNT
+};
+void smm_southcluster_save_param(int param, uint32_t data)
+
 /* Save settings which will be committed in SMI functions. */
 static uint32_t smm_save_params[SMM_SAVE_PARAM_COUNT];
-void southcluster_smm_save_param(int param, uint32_t data)
+void smm_southcluster_save_param(int param, uint32_t data)
 {
    smm_save_params[param] = data;
 }
-void southcluster_smm_clear_state(void)
+void smm_southbridge_clear_state(void)
 {
    uint32_t smi_en;
@@ -57,7 +64,7 @@
    clear_pmc_status();
 }
-static void southcluster_smm_route_gpios(void)
+static void smm_southcluster_route_gpios(void)
 {
    u32 *gpio_rout = (u32 *)(PMC_BASE_ADDRESS + GPIO_ROUT);
    const unsigned short alt_gpio_smi = ACPI_BASE_ADDRESS + ALT_GPIO_SMI;
@@ -82,7 +89,7 @@
    outl(alt_gpio_reg, alt_gpio_smi);
 }
-void southcluster_smm_enable_smi(void)
+void smm_southbridge_enable_smi(void)
 {
    uint16_t pm1_events = PWRBTN_EN | GBL_EN;
@@ -93,7 +100,7 @@
    disable_gpe(PME_B0_EN);
/* Set up the GPIO route. */
-	southcluster_smm_route_gpios();
+	smm_southcluster_route_gpios();
/* Enable SMI generation:
     *  - on APMC writes (io 0xb2)
diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c
index 3fcbf4c..86b35de 100644
--- a/src/soc/intel/braswell/cpu.c
+++ b/src/soc/intel/braswell/cpu.c
@@ -214,10 +214,10 @@
    .get_cpu_count = get_cpu_count,
    .get_smm_info = get_smm_info,
    .get_microcode_info = get_microcode_info,
-	.pre_mp_smm_init = southcluster_smm_clear_state,
+	.pre_mp_smm_init = smm_southbridge_clear_state,
    .per_cpu_smm_trigger = per_cpu_smm_trigger,
    .relocation_handler = relocation_handler,
-	.post_mp_init = southcluster_smm_enable_smi,
+	.post_mp_init = smm_southbridge_enable_smi,
 };
void soc_init_cpus(struct device *dev)
diff --git a/src/soc/intel/braswell/include/soc/smm.h b/src/soc/intel/braswell/include/soc/smm.h
index 93065a2..8b13789 100644
--- a/src/soc/intel/braswell/include/soc/smm.h
+++ b/src/soc/intel/braswell/include/soc/smm.h
@@ -1,34 +1 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Google Inc.
- * Copyright (C) 2015 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#ifndef _SOC_SMM_H_
-#define _SOC_SMM_H_
-
-
-#if ENV_RAMSTAGE
-#include <stdint.h>
-void southcluster_smm_clear_state(void);
-void southcluster_smm_enable_smi(void);
-void southcluster_smm_save_param(int param, uint32_t data);
-#endif
-
-enum {
-	SMM_SAVE_PARAM_GPIO_ROUTE = 0,
-	SMM_SAVE_PARAM_PCIE_WAKE_ENABLE,
-	SMM_SAVE_PARAM_COUNT
-};
-
-#endif /* _SOC_SMM_H_ */
diff --git a/src/soc/intel/braswell/smm.c b/src/soc/intel/braswell/smm.c
index fe681c9..b0ec6d1 100644
--- a/src/soc/intel/braswell/smm.c
+++ b/src/soc/intel/braswell/smm.c
@@ -23,17 +23,24 @@
 #include <device/pci.h>
 #include <soc/iomap.h>
 #include <soc/pm.h>
-#include <soc/smm.h>
+
+enum {
+	SMM_SAVE_PARAM_GPIO_ROUTE = 0,
+	SMM_SAVE_PARAM_PCIE_WAKE_ENABLE,
+	SMM_SAVE_PARAM_COUNT
+};
+
+void smm_southcluster_save_param(int param, uint32_t data);
/* Save settings which will be committed in SMI functions. */
 static uint32_t smm_save_params[SMM_SAVE_PARAM_COUNT];
-void southcluster_smm_save_param(int param, uint32_t data)
+void smm_southcluster_save_param(int param, uint32_t data)
 {
    smm_save_params[param] = data;
 }
-void southcluster_smm_clear_state(void)
+void smm_southbridge_clear_state(void)
 {
    uint32_t smi_en;
@@ -58,7 +65,7 @@
    clear_pmc_status();
 }
-static void southcluster_smm_route_gpios(void)
+static void smm_southcluster_route_gpios(void)
 {
    void *gpio_rout = (void *)(PMC_BASE_ADDRESS + GPIO_ROUT);
    const unsigned short alt_gpio_smi = ACPI_BASE_ADDRESS + ALT_GPIO_SMI;
@@ -82,7 +89,7 @@
    outl(alt_gpio_reg, alt_gpio_smi);
 }
-void southcluster_smm_enable_smi(void)
+void smm_southbridge_enable_smi(void)
 {
    uint16_t pm1_events = PWRBTN_EN | GBL_EN;
@@ -93,7 +100,7 @@
    disable_gpe(PME_B0_EN);
/* Set up the GPIO route. */
-	southcluster_smm_route_gpios();
+	smm_southcluster_route_gpios();
/*
     * Enable SMI generation:
diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c
index 5ccaeaf..1dcadbe 100644
--- a/src/soc/intel/broadwell/cpu.c
+++ b/src/soc/intel/broadwell/cpu.c
@@ -651,7 +651,7 @@
/* Now that all APs have been relocated as well as the BSP let SMIs
     * start flowing. */
-	southbridge_smm_enable_smi();
+	smm_southbridge_enable_smi();
/* Lock down the SMRAM space. */
    smm_lock();
diff --git a/src/soc/intel/broadwell/include/soc/smm.h b/src/soc/intel/broadwell/include/soc/smm.h
index 515ab18..484b2f8 100644
--- a/src/soc/intel/broadwell/include/soc/smm.h
+++ b/src/soc/intel/broadwell/include/soc/smm.h
@@ -20,23 +20,8 @@
 #include <cpu/x86/msr.h>
-
-void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
-				uintptr_t staggered_smbase);
-void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
-		size_t *smm_save_state_size);
-void smm_initialize(void);
-void smm_relocate(void);
-void smm_lock(void);
-
 /* These helpers are for performing SMM relocation. */
 void southbridge_trigger_smi(void);
 void southbridge_clear_smi_status(void);
-/* The initialization of the southbridge is split into 2 components. One is
- * for clearing the state in the SMM registers. The other is for enabling
- * SMIs. They are split so that other work between the 2 actions. */
-void southbridge_smm_clear_state(void);
-void southbridge_smm_enable_smi(void);
-
 #endif
diff --git a/src/soc/intel/broadwell/smi.c b/src/soc/intel/broadwell/smi.c
index 9aab0d1..fe3a27a 100644
--- a/src/soc/intel/broadwell/smi.c
+++ b/src/soc/intel/broadwell/smi.c
@@ -25,7 +25,7 @@
 #include <soc/pm.h>
 #include <soc/smm.h>
-void southbridge_smm_clear_state(void)
+void smm_southbridge_clear_state(void)
 {
    u32 smi_en;
@@ -47,7 +47,7 @@
    clear_gpe_status();
 }
-void southbridge_smm_enable_smi(void)
+void smm_southbridge_enable_smi(void)
 {
    printk(BIOS_DEBUG, "Enabling SMIs.\n");
    /* Configure events */
diff --git a/src/soc/intel/broadwell/smmrelocate.c b/src/soc/intel/broadwell/smmrelocate.c
index c3c2501..e1478d0 100644
--- a/src/soc/intel/broadwell/smmrelocate.c
+++ b/src/soc/intel/broadwell/smmrelocate.c
@@ -237,7 +237,7 @@
 void smm_initialize(void)
 {
    /* Clear the SMM state in the southbridge. */
-	southbridge_smm_clear_state();
+	smm_southbridge_clear_state();
/*
     * Run the relocation handler for on the BSP to check and set up
diff --git a/src/soc/intel/cannonlake/include/soc/smm.h b/src/soc/intel/cannonlake/include/soc/smm.h
index 88f8e7c..8b13789 100644
--- a/src/soc/intel/cannonlake/include/soc/smm.h
+++ b/src/soc/intel/cannonlake/include/soc/smm.h
@@ -1,35 +1 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2017 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#ifndef _SOC_SMM_H_
-#define _SOC_SMM_H_
-
-#include <stdint.h>
-#include <cpu/x86/msr.h>
-#include <cpu/x86/smm.h>
-#include <soc/gpio.h>
-
-
-
-void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
-				uintptr_t staggered_smbase);
-void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
-		size_t *smm_save_state_size);
-void smm_initialize(void);
-void smm_relocate(void);
-void smm_lock(void);
-
-#endif
diff --git a/src/soc/intel/common/block/include/intelblocks/smm.h b/src/soc/intel/common/block/include/intelblocks/smm.h
index 25ff8f4..74fbf08 100644
--- a/src/soc/intel/common/block/include/intelblocks/smm.h
+++ b/src/soc/intel/common/block/include/intelblocks/smm.h
@@ -30,7 +30,6 @@
  * for clearing the state in the SMM registers. The other is for enabling
  * SMIs.
  */
-void smm_southbridge_clear_state(void);
 void smm_southbridge_enable(uint16_t pm1_events);
#endif
diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c
index bda6d1d..e6bdd1c 100644
--- a/src/soc/intel/denverton_ns/cpu.c
+++ b/src/soc/intel/denverton_ns/cpu.c
@@ -254,7 +254,7 @@
     * Now that all APs have been relocated as well as the BSP let SMIs
     * start flowing.
     */
-	southcluster_smm_enable_smi();
+	smm_southbridge_enable_smi();
 }
/*
@@ -268,7 +268,7 @@
    .pre_mp_init = pre_mp_init,
    .get_cpu_count = get_cpu_count,
    .get_smm_info = get_smm_info,
-	.pre_mp_smm_init = southcluster_smm_clear_state,
+	.pre_mp_smm_init = smm_southbridge_clear_state,
    .relocation_handler = relocation_handler,
    .post_mp_init = post_mp_init,
 };
diff --git a/src/soc/intel/denverton_ns/include/soc/smm.h b/src/soc/intel/denverton_ns/include/soc/smm.h
index a020891..0444699 100644
--- a/src/soc/intel/denverton_ns/include/soc/smm.h
+++ b/src/soc/intel/denverton_ns/include/soc/smm.h
@@ -24,11 +24,4 @@
    uint32_t smrr_mask;
 };
-#if !defined(__PRE_RAM__) && !defined(__SMM___)
-#include <stdint.h>
-void southcluster_smm_clear_state(void);
-void southcluster_smm_enable_smi(void);
-void southcluster_smm_save_gpio_route(uint32_t route);
-#endif
-
 #endif /* _DENVERTON_NS_SMM_H_ */
diff --git a/src/soc/intel/denverton_ns/smm.c b/src/soc/intel/denverton_ns/smm.c
index 2df6994..f267485 100644
--- a/src/soc/intel/denverton_ns/smm.c
+++ b/src/soc/intel/denverton_ns/smm.c
@@ -28,12 +28,12 @@
 #include <soc/smm.h>
/* Save the gpio route register. The settings are committed from
- * southcluster_smm_enable_smi(). */
+ * smm_southbridge_enable_smi(). */
 static uint32_t gpio_route;
-void southcluster_smm_save_gpio_route(uint32_t route) { gpio_route = route; }
+void smm_southcluster_save_gpio_route(uint32_t route) { gpio_route = route; }
-void southcluster_smm_clear_state(void)
+void smm_southbridge_clear_state(void)
 {
    uint32_t smi_en;
@@ -54,7 +54,7 @@
    clear_pmc_status();
 }
-void southcluster_smm_enable_smi(void)
+void smm_southbridge_enable_smi(void)
 {
printk(BIOS_DEBUG, "Enabling SMIs.\n");
diff --git a/src/soc/intel/fsp_baytrail/cpu.c b/src/soc/intel/fsp_baytrail/cpu.c
index c9db8d5..595265b 100644
--- a/src/soc/intel/fsp_baytrail/cpu.c
+++ b/src/soc/intel/fsp_baytrail/cpu.c
@@ -153,7 +153,7 @@
 static void enable_smis(void)
 {
    if (CONFIG(HAVE_SMI_HANDLER))
-		southcluster_smm_enable_smi();
+		smm_southbridge_enable_smi();
 }
static const struct mp_ops mp_ops = {
@@ -161,7 +161,7 @@
    .get_cpu_count = get_cpu_count,
    .get_smm_info = get_smm_info,
    .get_microcode_info = get_microcode_info,
-	.pre_mp_smm_init = southcluster_smm_clear_state,
+	.pre_mp_smm_init = smm_southbridge_clear_state,
    .relocation_handler = relocation_handler,
    .post_mp_init = enable_smis,
 };
diff --git a/src/soc/intel/fsp_baytrail/include/soc/smm.h b/src/soc/intel/fsp_baytrail/include/soc/smm.h
index eb3158e..8b13789 100644
--- a/src/soc/intel/fsp_baytrail/include/soc/smm.h
+++ b/src/soc/intel/fsp_baytrail/include/soc/smm.h
@@ -1,27 +1 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Google Inc.
- * Copyright (C) 2014 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#ifndef _BAYTRAIL_SMM_H_
-#define _BAYTRAIL_SMM_H_
-
-#if !defined(__PRE_RAM__) && !defined(__SMM___)
-#include <stdint.h>
-void southcluster_smm_clear_state(void);
-void southcluster_smm_enable_smi(void);
-void southcluster_smm_save_gpio_route(uint32_t route);
-#endif
-
-#endif /* _BAYTRAIL_SMM_H_ */
diff --git a/src/soc/intel/fsp_baytrail/smm.c b/src/soc/intel/fsp_baytrail/smm.c
index df55433..995c26b 100644
--- a/src/soc/intel/fsp_baytrail/smm.c
+++ b/src/soc/intel/fsp_baytrail/smm.c
@@ -26,15 +26,15 @@
 #include <soc/smm.h>
/* Save the gpio route register. The settings are committed from
- * southcluster_smm_enable_smi(). */
+ * smm_southbridge_enable_smi(). */
 static uint32_t gpio_route;
-void southcluster_smm_save_gpio_route(uint32_t route)
+void smm_southcluster_save_gpio_route(uint32_t route)
 {
    gpio_route = route;
 }
-void southcluster_smm_clear_state(void)
+void smm_southbridge_clear_state(void)
 {
    uint32_t smi_en;
@@ -59,7 +59,7 @@
    clear_pmc_status();
 }
-static void southcluster_smm_route_gpios(void)
+static void smm_southcluster_route_gpios(void)
 {
    u32 *gpio_rout = (u32 *)(PMC_BASE_ADDRESS + GPIO_ROUT);
    const unsigned short alt_gpio_smi = ACPI_BASE_ADDRESS + ALT_GPIO_SMI;
@@ -84,7 +84,7 @@
    outl(alt_gpio_reg, alt_gpio_smi);
 }
-void southcluster_smm_enable_smi(void)
+void smm_southbridge_enable_smi(void)
 {
printk(BIOS_DEBUG, "Enabling SMIs.\n");
@@ -93,7 +93,7 @@
    disable_gpe(PME_B0_EN);
/* Set up the GPIO route. */
-	southcluster_smm_route_gpios();
+	smm_southcluster_route_gpios();
/* Enable SMI generation:
     *  - on APMC writes (io 0xb2)
diff --git a/src/soc/intel/fsp_broadwell_de/cpu.c b/src/soc/intel/fsp_broadwell_de/cpu.c
index 0b933c5..e721bfd 100644
--- a/src/soc/intel/fsp_broadwell_de/cpu.c
+++ b/src/soc/intel/fsp_broadwell_de/cpu.c
@@ -99,7 +99,7 @@
    set_max_ratio();
    /* Now that all APs have been relocated as well as the BSP let SMIs
       start flowing. */
-	southbridge_smm_enable_smi();
+	smm_southbridge_enable_smi();
/* Set SMI lock bits. */
    smm_lock();
diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/smm.h b/src/soc/intel/fsp_broadwell_de/include/soc/smm.h
index 990259f..1d46fe5 100644
--- a/src/soc/intel/fsp_broadwell_de/include/soc/smm.h
+++ b/src/soc/intel/fsp_broadwell_de/include/soc/smm.h
@@ -21,25 +21,8 @@
 #include <cpu/x86/msr.h>
-
-void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
-				uintptr_t staggered_smbase);
-void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
-		size_t *smm_save_state_size);
-void smm_initialize(void);
-void smm_relocate(void);
-void smm_lock(void);
-
 /* These helpers are for performing SMM relocation. */
 void southbridge_trigger_smi(void);
 void southbridge_clear_smi_status(void);
-/*
- * The initialization of the southbridge is split into 2 components. One is
- * for clearing the state in the SMM registers. The other is for enabling
- * SMIs. They are split so that other work between the 2 actions.
- */
-void southbridge_smm_clear_state(void);
-void southbridge_smm_enable_smi(void);
-
 #endif
diff --git a/src/soc/intel/fsp_broadwell_de/smi.c b/src/soc/intel/fsp_broadwell_de/smi.c
index 5411bca..5344390 100644
--- a/src/soc/intel/fsp_broadwell_de/smi.c
+++ b/src/soc/intel/fsp_broadwell_de/smi.c
@@ -21,7 +21,7 @@
 #include <soc/lpc.h>
 #include <soc/smm.h>
-void southbridge_smm_clear_state(void)
+void smm_southbridge_clear_state(void)
 {
    u32 smi_en;
@@ -41,7 +41,7 @@
    clear_pm1_status();
 }
-void southbridge_smm_enable_smi(void)
+void smm_southbridge_enable_smi(void)
 {
    printk(BIOS_DEBUG, "Enabling SMIs.\n");
diff --git a/src/soc/intel/fsp_broadwell_de/smmrelocate.c b/src/soc/intel/fsp_broadwell_de/smmrelocate.c
index a454a2e..1ef3860 100644
--- a/src/soc/intel/fsp_broadwell_de/smmrelocate.c
+++ b/src/soc/intel/fsp_broadwell_de/smmrelocate.c
@@ -257,7 +257,7 @@
 void smm_initialize(void)
 {
    /* Clear the SMM state in the southbridge. */
-	southbridge_smm_clear_state();
+	smm_southbridge_clear_state();
/* Run the relocation handler for on the BSP to check and set up
       parallel SMM relocation. */
diff --git a/src/soc/intel/icelake/include/soc/smm.h b/src/soc/intel/icelake/include/soc/smm.h
index 1091ff6..8b13789 100644
--- a/src/soc/intel/icelake/include/soc/smm.h
+++ b/src/soc/intel/icelake/include/soc/smm.h
@@ -1,34 +1 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2018 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#ifndef _SOC_SMM_H_
-#define _SOC_SMM_H_
-
-#include <stdint.h>
-#include <cpu/x86/msr.h>
-#include <cpu/x86/smm.h>
-#include <soc/gpio.h>
-
-
-
-void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
-				uintptr_t staggered_smbase);
-void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
-		size_t *smm_save_state_size);
-void smm_initialize(void);
-void smm_relocate(void);
-void smm_lock(void);
-
-#endif
diff --git a/src/soc/intel/skylake/include/soc/smm.h b/src/soc/intel/skylake/include/soc/smm.h
index a01ba14..8b13789 100644
--- a/src/soc/intel/skylake/include/soc/smm.h
+++ b/src/soc/intel/skylake/include/soc/smm.h
@@ -1,36 +1 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#ifndef _SOC_SMM_H_
-#define _SOC_SMM_H_
-
-#include <stdint.h>
-#include <cpu/x86/msr.h>
-#include <cpu/x86/smm.h>
-#include <intelblocks/smihandler.h>
-#include <soc/gpio.h>
-
-
-
-void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
-				uintptr_t staggered_smbase);
-void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
-		size_t *smm_save_state_size);
-void smm_initialize(void);
-void smm_relocate(void);
-void smm_lock(void);
-
-#endif
diff --git a/src/southbridge/intel/common/smi.c b/src/southbridge/intel/common/smi.c
index 398c680..1469fa4 100644
--- a/src/southbridge/intel/common/smi.c
+++ b/src/southbridge/intel/common/smi.c
@@ -123,7 +123,7 @@
    );
 }
-void southbridge_smm_clear_state(void)
+void smm_southbridge_clear_state(void)
 {
    u32 smi_en;
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
index 626d22d..fddab73 100644
--- a/src/southbridge/intel/lynxpoint/pch.h
+++ b/src/southbridge/intel/lynxpoint/pch.h
@@ -186,12 +186,10 @@
 /* These helpers are for performing SMM relocation. */
 void southbridge_trigger_smi(void);
 void southbridge_clear_smi_status(void);
-/* The initialization of the southbridge is split into 2 compoments. One is
- * for clearing the state in the SMM registers. The other is for enabling
- * SMIs. They are split so that other work between the 2 actions. */
-void southbridge_smm_clear_state(void);
-void southbridge_smm_enable_smi(void);
+
+
 #else
+
 void enable_smbus(void);
 void enable_usb_bar(void);
 int smbus_read_byte(unsigned device, unsigned address);
diff --git a/src/southbridge/intel/lynxpoint/smi.c b/src/southbridge/intel/lynxpoint/smi.c
index 3a6c4038..295d6f5 100644
--- a/src/southbridge/intel/lynxpoint/smi.c
+++ b/src/southbridge/intel/lynxpoint/smi.c
@@ -24,7 +24,7 @@
#include "pch.h"
-void southbridge_smm_clear_state(void)
+void smm_southbridge_clear_state(void)
 {
    u32 smi_en;
@@ -50,7 +50,7 @@
    clear_gpe_status();
 }
-void southbridge_smm_enable_smi(void)
+void smm_southbridge_enable_smi(void)
 {
    printk(BIOS_DEBUG, "Enabling SMIs.\n");
    /* Configure events */
-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I4f6f9207ba32cf51d75b9ca9230e38310a33a311
Gerrit-Change-Number: 34856
Gerrit-PatchSet: 1
Gerrit-Owner: Kyösti Mälkki kyosti.malkki@gmail.com
Gerrit-MessageType: newchange



    