Change in coreboot[master]: mb/adlrvp: Fix DDR5 Boot issue

[Subrata Banik (Code Review)]

Attention is currently required from: Bora Guvendik, Furquan Shaikh, Selma Bensaid, Maulik V Vaghela, Tim Wawrzynczak, Paul Menzel, Meera Ravindranath, Angel Pons, Patrick Rudolph.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50996 )

Change subject: mb/adlrvp: Fix DDR5 Boot issue
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Patch Set 20:

(1 comment)

File src/mainboard/intel/adlrvp/romstage_fsp_params.c:

https://review.coreboot.org/c/coreboot/+/50996/comment/7fa4a93f_bc37fc4a 
PS20, Line 56: 0xa0
note: you are taking complete 8 bit address and later if you implement DDR5 driver where you might need to pass 7 bit address as line:42. it might break as it happened for DDR4 earlier.

keeping this code as is there, might cause problem, why don't you still pass 7 bit address here and ddr5_fill_dimm_module_info() function takes care of shifting it while prior assigning into UPDs?