Attention is currently required from: Bill XIE. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52344 )
Change subject: mb/asus/p8z77-v_lx2: Add CMOS option support ......................................................................
Patch Set 4:
(9 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/52344/comment/e5324b29_0e4ef444 PS4, Line 10: to 400 I'd drop the CMOS offset.
Patchset:
PS4: Patchset 3 was fine...
File src/mainboard/asus/p8z77-v_lx2/cmos.default:
https://review.coreboot.org/c/coreboot/+/52344/comment/c698f915_a8463e38 PS4, Line 1: ## SPDX-License-Identifier: GPL-2.0-only Which code is licensed here?
https://review.coreboot.org/c/coreboot/+/52344/comment/df7e567c_1bb1cbc5 PS4, Line 10: #usb3_xxxx options are only used with MRC blob, ignored else This board selects `USE_NATIVE_RAMINIT`, which means using the MRC blob is currently not an option. Moreover, these options are only read in asus/p8z77-m_pro code.
File src/mainboard/asus/p8z77-v_lx2/cmos.layout:
https://review.coreboot.org/c/coreboot/+/52344/comment/c88c9e26_264fdb70 PS4, Line 20: 400 1 e 1 hyper_threading Where is this used?
https://review.coreboot.org/c/coreboot/+/52344/comment/29de567a_12a36a26 PS4, Line 26: # occur on a RAM or unrecoverable error. Documentation about southbridge options should not be in every mainboard's cmos.layout file.
https://review.coreboot.org/c/coreboot/+/52344/comment/de576e4a_65404e8b PS4, Line 40: # ----------------------------------------------------------------- : # coreboot config options: usb3 : : # usb3_mode : # Controls how the motherboard's USB3 ports act at boot time : 421 2 e 7 usb3_mode : : # usb3_drv : # Load (or not) pre-OS xHCI USB3 BIOS driver : # : 423 1 e 1 usb3_drv : : # usb3_streams : # Streams can provide more speed (as they can use 64Kb packets), : # but they might cause incompatibilities with some devices. : # : 424 1 e 1 usb3_streams Where is this used?
https://review.coreboot.org/c/coreboot/+/52344/comment/af19ec67_18bdbc66 PS4, Line 59: # Sandy/Ivy Bridge MRC Scrambler Seed values : # note: MUST NOT be covered by checksum! : 464 32 r 0 mrc_scrambler_seed : 496 32 r 0 mrc_scrambler_seed_s3 : 528 16 r 0 mrc_scrambler_seed_chk Where is this used?
https://review.coreboot.org/c/coreboot/+/52344/comment/bfe86e84_12550766 PS4, Line 151: # <bit where to start storing checksum[must be 16bits-aligned]> If the cmos.layout format is so cryptic, why not improve it?
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Angel Pons (Code Review)