Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40972 )
Change subject: nb/intel/sandybridge: Reorder register write ......................................................................
nb/intel/sandybridge: Reorder register write
Reorder the order of the operands in three register writes, so that replacing them with macros in a follow-up does not change the binary.
Change-Id: I44aee9c0f49770586de322ee7f44c3609dbadd0b Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/40972/1
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 087ba2b..d97632e 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -668,21 +668,21 @@ MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = IOSAV_MRS & NO_RANKSEL; MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0x41001; MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = - (slotrank << 24) | (reg << 20) | val | 0x60000; + val | 0x60000 | (reg << 20) | (slotrank << 24); MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0;
/* DRAM command MRS */ MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = IOSAV_MRS; MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = 0x41001; MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = - (slotrank << 24) | (reg << 20) | val | 0x60000; + val | 0x60000 | (reg << 20) | (slotrank << 24); MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0;
/* DRAM command MRS */ MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = IOSAV_MRS & NO_RANKSEL; MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 2)) = 0x1001 | (ctrl->tMOD << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = - (slotrank << 24) | (reg << 20) | val | 0x60000; + val | 0x60000 | (reg << 20) | (slotrank << 24); MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 2)) = 0;
/* Execute command queue */
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40972 )
Change subject: nb/intel/sandybridge: Reorder register write ......................................................................
Patch Set 1: Code-Review+2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40972 )
Change subject: nb/intel/sandybridge: Reorder register write ......................................................................
Patch Set 1: Code-Review-2
Untested, blocking just in case
Hello build bot (Jenkins), Patrick Rudolph, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40972
to look at the new patch set (#4).
Change subject: nb/intel/sandybridge: Reorder register write ......................................................................
nb/intel/sandybridge: Reorder register write
Reorder the order of the operands in three register writes, so that replacing them with macros in a follow-up does not change the binary.
Tested on Asus P8Z77-V LX2, still boots.
Change-Id: I44aee9c0f49770586de322ee7f44c3609dbadd0b Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/40972/4
Angel Pons has removed a vote from this change. ( https://review.coreboot.org/c/coreboot/+/40972 )
Change subject: nb/intel/sandybridge: Reorder register write ......................................................................
Removed Code-Review-2 by Angel Pons th3fanbus@gmail.com
Patrick Rudolph has submitted this change. ( https://review.coreboot.org/c/coreboot/+/40972 )
Change subject: nb/intel/sandybridge: Reorder register write ......................................................................
nb/intel/sandybridge: Reorder register write
Reorder the order of the operands in three register writes, so that replacing them with macros in a follow-up does not change the binary.
Tested on Asus P8Z77-V LX2, still boots.
Change-Id: I44aee9c0f49770586de322ee7f44c3609dbadd0b Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/40972 Reviewed-by: Felix Held felix-coreboot@felixheld.de Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 3 insertions(+), 3 deletions(-)
Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 19b72cb..34d82fc 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -667,21 +667,21 @@ MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = IOSAV_MRS & NO_RANKSEL; MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0x41001; MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = - (slotrank << 24) | (reg << 20) | val | 0x60000; + val | 0x60000 | (reg << 20) | (slotrank << 24); MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0;
/* DRAM command MRS */ MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = IOSAV_MRS; MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = 0x41001; MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = - (slotrank << 24) | (reg << 20) | val | 0x60000; + val | 0x60000 | (reg << 20) | (slotrank << 24); MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0;
/* DRAM command MRS */ MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = IOSAV_MRS & NO_RANKSEL; MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 2)) = 0x1001 | (ctrl->tMOD << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = - (slotrank << 24) | (reg << 20) | val | 0x60000; + val | 0x60000 | (reg << 20) | (slotrank << 24); MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 2)) = 0;
/* Execute command queue */
-
Angel Pons (Code Review) -
Felix Held (Code Review)
-
Patrick Rudolph (Code Review)