Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43912 )
Change subject: mb/intel/kblrvp/var/rvp3: Relocate devicetree FSP settings ......................................................................
mb/intel/kblrvp/var/rvp3: Relocate devicetree FSP settings
Tested with BUILD_TIMELESS=1, its coreboot.rom does not change.
Change-Id: I9988c8d26c5c27973a9877a0f0e3e0d51513bd92 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb 1 file changed, 40 insertions(+), 48 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/43912/1
diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb index 4765c81..68430c9 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb @@ -7,11 +7,9 @@ register "gen2_dec" = "0x000c0201"
# FSP Configuration - register "EnableAzalia" = "1" - register "DspEnable" = "1" + register "DspEnable" = "1" register "PmTimerDisabled" = "1" register "Cio2Enable" = "1" - register "SaImguEnable" = "1"
# VR Settings Configuration for 4 Domains #+----------------+-------+-------+-------+-------+ @@ -40,44 +38,6 @@ .voltage_limit = 1520 \ }"
- # Enable Root ports. - # PCIE Port 1 x4 -> SLOT1 - register "PcieRpEnable[0]" = "1" - register "PcieRpClkReqSupport[0]" = "1" - register "PcieRpClkReqNumber[0]" = "2" - # RP1, uses uses CLK SRC 2 - register "PcieRpClkSrcNumber[0]" = "2" - - # PCIE Port 5 x1 -> SLOT2/LAN - register "PcieRpEnable[4]" = "1" - register "PcieRpClkReqSupport[4]" = "1" - register "PcieRpClkReqNumber[4]" = "3" - # RP5, uses uses CLK SRC 3 - register "PcieRpClkSrcNumber[4]" = "3" - - # PCIE Port 6 x1 -> SLOT3 - register "PcieRpEnable[5]" = "1" - register "PcieRpClkReqSupport[5]" = "1" - register "PcieRpClkReqNumber[5]" = "1" - # RP6, uses uses CLK SRC 1 - register "PcieRpClkSrcNumber[5]" = "1" - - # PCIE Port 7 Disabled - # PCIE Port 8 Disabled - # PCIE Port 9 x1 -> WLAN - register "PcieRpEnable[8]" = "1" - register "PcieRpClkReqSupport[8]" = "1" - register "PcieRpClkReqNumber[8]" = "5" - # RP9, uses uses CLK SRC 5 - register "PcieRpClkSrcNumber[8]" = "5" - - # PCIE Port 10 x1 -> WiGig - register "PcieRpEnable[9]" = "1" - register "PcieRpClkReqSupport[9]" = "1" - register "PcieRpClkReqNumber[9]" = "4" - # RP10, uses uses CLK SRC 4 - register "PcieRpClkSrcNumber[9]" = "4" - # USB 2.0 Enable all ports register "usb2_ports[0]" = "USB2_PORT_MAX(OC0)" # TYPE-A Port register "usb2_ports[1]" = "USB2_PORT_MAX(OC2)" # TYPE-A Port @@ -96,8 +56,8 @@ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)" # TYPE-A Port - register "usb3_ports[4]" = "USB3_PORT_EMPTY" # Disabled - register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Disabled + register "usb3_ports[4]" = "USB3_PORT_EMPTY" # Disabled + register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Disabled
register "SsicPortEnable" = "1" # Enable SSIC for WWAN
@@ -122,15 +82,47 @@ }"
device domain 0 on - device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1 - device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN - device pci 1c.5 on end # PCI Express Port 6 x1 SLOT3 - device pci 1d.0 on end # PCI Express Port 9 x1 WLAN - device pci 1d.1 on end # PCI Express Port 10 x1 WIGIG + + # FIXME: corresponding device entry is missing + register "SaImguEnable" = "1" + + device pci 1c.0 on # PCI Express Port 1 x4 SLOT1 + register "PcieRpEnable[0]" = "1" + register "PcieRpClkReqSupport[0]" = "1" + register "PcieRpClkReqNumber[0]" = "2" + register "PcieRpClkSrcNumber[0]" = "2" + end + device pci 1c.4 on # PCI Express Port 5 x1 SLOT2/LAN + register "PcieRpEnable[4]" = "1" + register "PcieRpClkReqSupport[4]" = "1" + register "PcieRpClkReqNumber[4]" = "3" + register "PcieRpClkSrcNumber[4]" = "3" + end + device pci 1c.5 on # PCI Express Port 6 x1 SLOT3 + register "PcieRpEnable[5]" = "1" + register "PcieRpClkReqSupport[5]" = "1" + register "PcieRpClkReqNumber[5]" = "1" + register "PcieRpClkSrcNumber[5]" = "1" + end + device pci 1d.0 on # PCI Express Port 9 x1 WLAN + register "PcieRpEnable[8]" = "1" + register "PcieRpClkReqSupport[8]" = "1" + register "PcieRpClkReqNumber[8]" = "5" + register "PcieRpClkSrcNumber[8]" = "5" + end + device pci 1d.1 on # PCI Express Port 10 x1 WIGIG + register "PcieRpEnable[9]" = "1" + register "PcieRpClkReqSupport[9]" = "1" + register "PcieRpClkReqNumber[9]" = "4" + register "PcieRpClkSrcNumber[9]" = "4" + end device pci 1f.0 on chip drivers/pc80/tpm device pnp 0c31.0 on end end end # LPC Interface + + # Enable Intel HD + register "EnableAzalia" = "1" end end
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43912
to look at the new patch set (#3).
Change subject: mb/intel/kblrvp/var/rvp3: Relocate devicetree settings ......................................................................
mb/intel/kblrvp/var/rvp3: Relocate devicetree settings
Tested with BUILD_TIMELESS=1, its coreboot.rom does not change.
Change-Id: I9988c8d26c5c27973a9877a0f0e3e0d51513bd92 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb 1 file changed, 40 insertions(+), 48 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/43912/3
Angel Pons has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/43912 )
Change subject: mb/intel/kblrvp/var/rvp3: Relocate devicetree settings ......................................................................
Abandoned
-
Angel Pons (Code Review)