Attention is currently required from: Arthur Heymans, Christian Walter, Felix Held, Johnny Lin, Nico Huber, Patrick Rudolph, Shuo Liu, Tim Chu.
Hello Arthur Heymans, Christian Walter, Felix Held, Johnny Lin, Lean Sheng Tan, Nico Huber, Shuo Liu, Tim Chu, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/80548?usp=email
to look at the new patch set (#3).
The following approvals got outdated and were removed: Code-Review+1 by Shuo Liu, Verified+1 by build bot (Jenkins)
Change subject: soc/intel/xeon_sp: Align resources to 4K ......................................................................
soc/intel/xeon_sp: Align resources to 4K
The lower bit of the BAR might be used for something else, like enable bits, so mask the lower 12 bits and align all base address to 4K.
Confirmed that all BARs have a minimum alignment of 4K, so that masking the lower bits doesn't change the reported address.
The alignment of the VTD BARs is: - VTD_MMCFG_BASE_CSR 64 MiB - VTD_MMIOL_CSR 1 MiB - VTD_NCMEM_BASE_CSR 64 MiB - VTD_TSEG_BASE_CSR 1 MiB - VTD_BAR_CSR 4 KiB
Change-Id: I9a7b963c0074246616968dd15c147f4916297d59 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M src/soc/intel/xeon_sp/include/soc/iomap.h M src/soc/intel/xeon_sp/uncore.c 2 files changed, 2 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/80548/3