Change in coreboot[master]: soc/intel/alderlake: Add definition for virtual GPIOs

[Sugnan Prabhu S (Code Review)]

Attention is currently required from: Furquan Shaikh, Maulik V Vaghela, Subrata Banik, Patrick Rudolph.
Sugnan Prabhu S has uploaded a new patch set (#6) to the change originally created by Maulik V Vaghela. ( https://review.coreboot.org/c/coreboot/+/55270 )

Change subject: soc/intel/alderlake: Add definition for virtual GPIOs
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soc/intel/alderlake: Add definition for virtual GPIOs

Alder Lake SoC has virtual GPIOs for community 1 which was being
programmed by FSP and hence was skipped by coreboot. As part of
moving most of the GPIO programming to coreboot, we're skipping this
programming in FSP now.

TEST=Check register offset to see if programming is correct.

Change-Id: I4d48553d14465df50e5aaaf27ab26c6a1b70d4cf
Signed-off-by: Maulik V Vaghela 
---
M src/soc/intel/alderlake/gpio.c
M src/soc/intel/alderlake/include/soc/gpio_soc_defs.h
2 files changed, 281 insertions(+), 223 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/55270/6