Change in coreboot[master]: soc/intel/skylake: Enable HECI3 depending on devicetree configuration
Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43864 )
Change subject: soc/intel/skylake: Enable HECI3 depending on devicetree configuration ......................................................................
soc/intel/skylake: Enable HECI3 depending on devicetree configuration
Currently HECI3 gets enabled by the option Heci3Enabled, but this duplicates the devicetree on/off options. Therefore use the on/off options for the enablement of the HECI3 controller.
I checked all corresponding mainboards if the devicetree configuration matches the Heci3Enabled setting.
Change-Id: I4f99d434dfee49a9783e38c3910b9391d479cb83 Signed-off-by: Felix Singer felixsinger@posteo.net --- M src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb M src/mainboard/intel/saddlebrook/devicetree.cb M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip.h 4 files changed, 3 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/43864/1
diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb index bff7967..b7b569d7 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb @@ -7,7 +7,6 @@ register "ScsEmmcHs400Enabled" = "0" register "ScsSdCardEnabled" = "0" register "Device4Enable" = "0" - register "Heci3Enabled" = "0" register "PmTimerDisabled" = "0"
register "serirq_mode" = "SERIRQ_CONTINUOUS" diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb index 8fa12ec..defb5e3 100644 --- a/src/mainboard/intel/saddlebrook/devicetree.cb +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -25,7 +25,6 @@ register "ScsSdCardEnabled" = "0" register "SkipExtGfxScan" = "1" register "Device4Enable" = "0" - register "Heci3Enabled" = "0"
register "SaGv" = "SaGv_Enabled" register "PmTimerDisabled" = "0" diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index c5d1392..fcc8840 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -231,7 +231,9 @@
params->PchCio2Enable = config->Cio2Enable; params->SaImguEnable = config->SaImguEnable; - params->Heci3Enabled = config->Heci3Enabled; + + dev = pcidev_path_on_root(PCH_DEVFN_CSE_3); + params->Heci3Enabled = dev ? dev->enabled : 0;
params->LogoPtr = config->LogoPtr; params->LogoSize = config->LogoSize; diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 785e3e0..8906efd0 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -328,7 +328,6 @@ u8 PttSwitch; u8 HeciTimeouts; u8 HsioMessaging; - u8 Heci3Enabled;
/* Gfx related */ u8 IgdDvmt50PreAlloc;
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43864 )
Change subject: soc/intel/skylake: Enable HECI3 depending on devicetree configuration ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43864/2/src/soc/intel/skylake/chip.... File src/soc/intel/skylake/chip.c:
https://review.coreboot.org/c/coreboot/+/43864/2/src/soc/intel/skylake/chip.... PS2, Line 234: Heci3Enabled there is more than one heci device; HeciEnabled exists, too
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43864
to look at the new patch set (#5).
Change subject: soc/intel/skylake: Enable HECI3 depending on devicetree configuration ......................................................................
soc/intel/skylake: Enable HECI3 depending on devicetree configuration
Currently HECI3 gets enabled by the option Heci3Enabled, but this duplicates the devicetree on/off options. Therefore use the on/off options for the enablement of the HECI3 controller.
I checked all corresponding mainboards if the devicetree configuration matches the Heci3Enabled setting.
Change-Id: I4f99d434dfee49a9783e38c3910b9391d479cb83 Signed-off-by: Felix Singer felixsinger@posteo.net --- M src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb M src/mainboard/intel/saddlebrook/devicetree.cb M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip.h 4 files changed, 3 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/43864/5
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43864 )
Change subject: soc/intel/skylake: Enable HECI3 depending on devicetree configuration ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43864/2/src/soc/intel/skylake/chip.... File src/soc/intel/skylake/chip.c:
https://review.coreboot.org/c/coreboot/+/43864/2/src/soc/intel/skylake/chip.... PS2, Line 234: Heci3Enabled
there is more than one heci device; HeciEnabled exists, too
I will upload another patch for this option later.
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43864 )
Change subject: soc/intel/skylake: Enable HECI3 depending on devicetree configuration ......................................................................
Patch Set 5: Code-Review+2
Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/43864 )
Change subject: soc/intel/skylake: Enable HECI3 depending on devicetree configuration ......................................................................
soc/intel/skylake: Enable HECI3 depending on devicetree configuration
Currently HECI3 gets enabled by the option Heci3Enabled, but this duplicates the devicetree on/off options. Therefore use the on/off options for the enablement of the HECI3 controller.
I checked all corresponding mainboards if the devicetree configuration matches the Heci3Enabled setting.
Change-Id: I4f99d434dfee49a9783e38c3910b9391d479cb83 Signed-off-by: Felix Singer felixsinger@posteo.net Reviewed-on: https://review.coreboot.org/c/coreboot/+/43864 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb M src/mainboard/intel/saddlebrook/devicetree.cb M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip.h 4 files changed, 3 insertions(+), 4 deletions(-)
Approvals: build bot (Jenkins): Verified Michael Niewöhner: Looks good to me, approved
diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb index bff7967..b7b569d7 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb @@ -7,7 +7,6 @@ register "ScsEmmcHs400Enabled" = "0" register "ScsSdCardEnabled" = "0" register "Device4Enable" = "0" - register "Heci3Enabled" = "0" register "PmTimerDisabled" = "0"
register "serirq_mode" = "SERIRQ_CONTINUOUS" diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb index 944cb50..a8066d5 100644 --- a/src/mainboard/intel/saddlebrook/devicetree.cb +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -25,7 +25,6 @@ register "ScsSdCardEnabled" = "0" register "SkipExtGfxScan" = "1" register "Device4Enable" = "0" - register "Heci3Enabled" = "0"
register "SaGv" = "SaGv_Enabled" register "PmTimerDisabled" = "0" diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 7dee333..a73aa8d 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -231,7 +231,9 @@
params->PchCio2Enable = config->Cio2Enable; params->SaImguEnable = config->SaImguEnable; - params->Heci3Enabled = config->Heci3Enabled; + + dev = pcidev_path_on_root(PCH_DEVFN_CSE_3); + params->Heci3Enabled = dev ? dev->enabled : 0;
params->LogoPtr = config->LogoPtr; params->LogoSize = config->LogoSize; diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 54d0069..3f55c18 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -315,7 +315,6 @@ u8 PttSwitch; u8 HeciTimeouts; u8 HsioMessaging; - u8 Heci3Enabled;
/* Gfx related */ u8 IgdDvmt50PreAlloc;
-
Felix Singer (Code Review) -
Michael Niewöhner (Code Review)