Change in coreboot[master]: cpu/intel/car/romstage.c: Drop superfluous code

[Keith Hui (Code Review)]

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/21347

Change subject: cpu/intel/car/romstage.c: Drop superfluous code
......................................................................

cpu/intel/car/romstage.c: Drop superfluous code

Both functions are never called under their intended configurations.

The setup_stack_and_mtrrs() here guarded by LATE_CBMEM_INIT may even
get in the way of versions implemented elsewhere as boards move to
EARLY_CBMEM_INIT.

Boot tested on asus/p2b-ls with [1] applied. It is therefore
strongly recommended that it be merged before this.

[1] https://review.coreboot.org/c/21313/

Change-Id: I8ac0f4c2a4642712df062f8b9001d912c7612d9a
Signed-off-by: Keith Hui 
---
M src/cpu/intel/car/romstage.c
1 file changed, 0 insertions(+), 29 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/21347/1

diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c
index 1477612..828b171 100644
--- a/src/cpu/intel/car/romstage.c
+++ b/src/cpu/intel/car/romstage.c
@@ -46,32 +46,3 @@

return romstage_stack_after_car;
 }
-
-asmlinkage void romstage_after_car(void)
-{
-	/* Load the ramstage. */
-	run_ramstage();
-}
-
-#if IS_ENABLED(CONFIG_LATE_CBMEM_INIT)
-/* setup_stack_and_mtrrs() determines the stack to use after
- * cache-as-ram is torn down as well as the MTRR settings to use. */
-void *setup_stack_and_mtrrs(void)
-{
-	struct postcar_frame pcf;
-
-	postcar_frame_init_lowmem(&pcf);
-
-	/* Cache the ROM as WP just below 4GiB. */
-	postcar_frame_add_mtrr(&pcf, -CACHE_ROM_SIZE, CACHE_ROM_SIZE,
-		MTRR_TYPE_WRPROT);
-
-	/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
-	postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
-
-	/* Save the number of MTRRs to setup. Return the stack location
-	 * pointing to the number of MTRRs.
-	 */
-	return postcar_commit_mtrrs(&pcf);
-}
-#endif /* CONFIG_LATE_CBMEM_INIT */