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Subrata Banik has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/83789?usp=email )
Change subject: soc/intel/ptl: Add GPIOs for Panther Lake SOC
......................................................................
Patch Set 45:
(1 comment)
File src/soc/intel/pantherlake/gpio.c:
https://review.coreboot.org/c/coreboot/+/83789/comment/70dfba2b_a35f11e8?usp... :
PS17, Line 54: .port = PID_GPIOCOM0,
in MTL, we have:
IOM_AUX_ORI_BIAS_CTRL_PUP[0] 0x1070
7:0 RW 0x0 GROUP_ID Group ID in PCH GPIO
10:8 RW 0x0 BIT_NUM Data bit Position in PCH GPIO
23:16 RW 0x0 VW_INDEX VW Index in PCH GPIO
In that case, all you need to do is submit a new Kconfig to support 16-bit CPU ports. You will need to specify SEGMENTID_CHIPSET0 in one more Kconfig, which may be SoC-specific. Then, before creating the PTL GPIO CL, add support for new 16-bit CPU port IDs in the tcss.c code.
The GPIO CL for PTL will simply add the CPU port number in the same way as MTL and other SoCs. The only thing that sets it apart is the new Kconfig that adds 16-bit support.
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