[L] Change in coreboot[main]: soc/mediatek/mt8189: Add a stub implementation of MT8189 SoC

[Vince Liu (Code Review)]

Vince Liu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85616?usp=email )

Change subject: soc/mediatek/mt8189: Add a stub implementation of MT8189 SoC
......................................................................

soc/mediatek/mt8189: Add a stub implementation of MT8189 SoC

Add new folder and basic drivers for Mediatek SoC 'MT8189'.
Also enable UART and ARM arch timer.

BUG=b:379008996
BRANCH=none
TEST=saw the coreboot uart log to bootblock

Change-Id: I5d83c4c7fba49e455fac0b58f019ad225f83c197
Signed-off-by: Vince Liu 
---
A src/soc/mediatek/mt8189/Kconfig
A src/soc/mediatek/mt8189/Makefile.mk
A src/soc/mediatek/mt8189/bootblock.c
A src/soc/mediatek/mt8189/include/soc/addressmap.h
A src/soc/mediatek/mt8189/include/soc/memlayout.ld
A src/soc/mediatek/mt8189/include/soc/pll.h
A src/soc/mediatek/mt8189/include/soc/spi.h
A src/soc/mediatek/mt8189/include/soc/timer.h
A src/soc/mediatek/mt8189/soc.c
A src/soc/mediatek/mt8189/spi.c
A src/soc/mediatek/mt8189/timer.c
11 files changed, 300 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/85616/1

diff --git a/src/soc/mediatek/mt8189/Kconfig b/src/soc/mediatek/mt8189/Kconfig
new file mode 100644
index 0000000..8d4e009
--- /dev/null
+++ b/src/soc/mediatek/mt8189/Kconfig
@@ -0,0 +1,22 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+config SOC_MEDIATEK_MT8189
+	bool
+	default n
+	select ARCH_BOOTBLOCK_ARMV8_64
+	select ARCH_VERSTAGE_ARMV8_64
+	select ARCH_ROMSTAGE_ARMV8_64
+	select ARCH_RAMSTAGE_ARMV8_64
+	select HAVE_UART_SPECIAL
+	select SOC_MEDIATEK_COMMON
+	select ARM64_USE_ARCH_TIMER
+
+if SOC_MEDIATEK_MT8189
+
+config VBOOT
+	select VBOOT_MUST_REQUEST_DISPLAY
+	select VBOOT_STARTS_IN_BOOTBLOCK
+	select VBOOT_SEPARATE_VERSTAGE
+	select VBOOT_RETURN_FROM_VERSTAGE
+
+endif
diff --git a/src/soc/mediatek/mt8189/Makefile.mk b/src/soc/mediatek/mt8189/Makefile.mk
new file mode 100644
index 0000000..55f4fec
--- /dev/null
+++ b/src/soc/mediatek/mt8189/Makefile.mk
@@ -0,0 +1,24 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+ifeq ($(CONFIG_SOC_MEDIATEK_MT8189),y)
+
+all-$(CONFIG_SPI_FLASH) += spi.c
+all-y += timer.c
+all-y += ../common/uart.c
+
+bootblock-y += bootblock.c
+bootblock-y += ../common/mmu_operations.c
+
+romstage-y += ../common/cbmem.c
+romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c
+
+ramstage-y += soc.c
+ramstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c
+
+CPPFLAGS_common += -Isrc/soc/mediatek/common/include
+CPPFLAGS_common += -Isrc/soc/mediatek/mt8189/include
+
+$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin
+	./util/mtkheader/gen-bl-img.py mt8189 sf $< $@
+
+endif
diff --git a/src/soc/mediatek/mt8189/bootblock.c b/src/soc/mediatek/mt8189/bootblock.c
new file mode 100644
index 0000000..f48e78c
--- /dev/null
+++ b/src/soc/mediatek/mt8189/bootblock.c
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <soc/mmu_operations.h>
+
+void bootblock_soc_init(void)
+{
+	mtk_mmu_init();
+}
diff --git a/src/soc/mediatek/mt8189/include/soc/addressmap.h b/src/soc/mediatek/mt8189/include/soc/addressmap.h
new file mode 100644
index 0000000..c0c78b1
--- /dev/null
+++ b/src/soc/mediatek/mt8189/include/soc/addressmap.h
@@ -0,0 +1,59 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#ifndef __SOC_MEDIATEK_MT8189_INCLUDE_SOC_ADDRESSMAP_H__
+#define __SOC_MEDIATEK_MT8189_INCLUDE_SOC_ADDRESSMAP_H__
+
+enum {
+	IO_PHYS = 0x10000000,
+};
+
+enum {
+	CKSYS_BASE			= IO_PHYS + 0x00000000,
+	INFRACFG_AO_BASE		= IO_PHYS + 0x00001000,
+	GPIO_BASE			= IO_PHYS + 0x00005000,
+	APMIXED_BASE			= IO_PHYS + 0x0000C000,
+	DEVAPC_INFRA_SECU_AO_BASE	= IO_PHYS + 0x0001C000,
+	BCRM_INFRA_AO_BASE		= IO_PHYS + 0x00022000,
+	DEVAPC_INFRA_AO_BASE		= IO_PHYS + 0x00030000,
+	DEVAPC_INFRA_AO1_BASE		= IO_PHYS + 0x00034000,
+	EMI0_BASE			= IO_PHYS + 0x00219000,
+	EMI0_MPU_BASE			= IO_PHYS + 0x00226000,
+	DRAMC_CHA_AO_BASE		= IO_PHYS + 0x00230000,
+	THERM_CTRL_BASE			= IO_PHYS + 0x00315000,
+	DPM_PM_SRAM_BASE		= IO_PHYS + 0x00900000,
+	DPM_DM_SRAM_BASE		= IO_PHYS + 0x00920000,
+	DPM_CFG_BASE			= IO_PHYS + 0x00940000,
+	DPM_PM_SRAM_BASE2		= IO_PHYS + 0x00A00000,
+	DPM_DM_SRAM_BASE2		= IO_PHYS + 0x00A20000,
+	DPM_CFG_BASE2			= IO_PHYS + 0x00A40000,
+	UART0_BASE			= IO_PHYS + 0x01001000,
+	SFLASH_REG_BASE			= IO_PHYS + 0x01018000,
+	PERICFG_AO_BASE			= IO_PHYS + 0x01036000,
+	DEVAPC_PERI_PAR_AO_BASE		= IO_PHYS + 0x0103C000,
+	SSUSB_IPPC_BASE			= IO_PHYS + 0x01203E00,
+	UFSHCI_BASE			= IO_PHYS + 0x012B0000,
+	MIPITX0_BASE			= IO_PHYS + 0x01B40000,
+	IOCFG_LM_BASE			= IO_PHYS + 0x01B50000,
+	EDP_BASE			= IO_PHYS + 0x01B70000,
+	IOCFG_RB0_BASE			= IO_PHYS + 0x01C50000,
+	IOCFG_RB1_BASE			= IO_PHYS + 0x01C60000,
+	IOCFG_BM0_BASE			= IO_PHYS + 0x01D20000,
+	IOCFG_BM1_BASE			= IO_PHYS + 0x01D30000,
+	IOCFG_BM2_BASE			= IO_PHYS + 0x01D40000,
+	IOCFG_LT0_BASE			= IO_PHYS + 0x01E20000,
+	IOCFG_LT1_BASE			= IO_PHYS + 0x01E30000,
+	SSUSB_SIF_BASE			= IO_PHYS + 0x01E80300,
+	IOCFG_RT_BASE			= IO_PHYS + 0x01F20000,
+	DSI0_BASE			= IO_PHYS + 0x04016000,
+	DISP_DVO0			= IO_PHYS + 0x04019000,
+	RGU_BASE			= IO_PHYS + 0x0C00A000,
+	SPMI_MST_BASE			= IO_PHYS + 0x0C013000,
+	DEVAPC_VLP_AO_BASE		= IO_PHYS + 0x0C018000,
+	SPMI_MST_P_BASE			= IO_PHYS + 0x0CC00000,
+	PMIF_SPMI_BASE			= IO_PHYS + 0x0CC04000,
+	PMIF_SPMI_P_BASE		= IO_PHYS + 0x0CC06000,
+	SYSTIMER_BASE			= IO_PHYS + 0x0CC10000,
+	DEVAPC_MM_AO_BASE		= IO_PHYS + 0x0E820000,
+};
+
+#endif /* __SOC_MEDIATEK_MT8189_INCLUDE_SOC_ADDRESSMAP_H__ */
diff --git a/src/soc/mediatek/mt8189/include/soc/memlayout.ld b/src/soc/mediatek/mt8189/include/soc/memlayout.ld
new file mode 100644
index 0000000..d0ef21a
--- /dev/null
+++ b/src/soc/mediatek/mt8189/include/soc/memlayout.ld
@@ -0,0 +1,70 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#include <soc/memlayout.h>
+
+SECTIONS
+{
+	/* MT8189 has 64KB SRAM. */
+	SRAM_START(0x00100000)
+	WATCHDOG_TOMBSTONE(0x00100030, 4)
+
+	/*
+	 * MCUPM uses the following regions to exchange data with kernel.
+	 * The addresses is hardcoded in MCUPM image.
+	 */
+	REGION(dvfs1_reserved, 0x00100a00, 3K, 4)
+	REGION(cpucooler_reserved, 0x00101600, 700, 4)
+	REGION(mcdi_reserved, 0x00101d00, 2K, 4)
+	REGION(thermal_reserved, 0x00102500, 1K, 4)
+	REGION(dvfs2_reserved, 0x00108D68, 5K, 4)
+	REGION(ptp1_reserved, 0x0010A168, 6808, 4)
+
+	/*
+	* Since MCUPM uses most of the space, most regions are put in SRAM_L2C below.
+	*/
+
+	SRAM_END(0x00110000)
+
+	/*
+	 * The L3 (can be used as SRAM_L2C) currently using is 1MB.
+	 * The BootROM has configured all cache as SRAM so we can't use them
+	 * unless if we disable L2C and reconfigure.
+	 */
+	SRAM_L2C_START(0x02000000)
+	#if ENV_ROMSTAGE
+	/*
+	* The needed size can be obtained by:
+	*  aarch64-cros-linux-gnu-objdump -x dram.elf | grep memsz
+	* To move the address, dram.elf also needs to be modified accordingly.
+	*/
+	DRAM_INIT_CODE(0x02000000, 500K)
+	#else
+	/*
+	* The bootROM needs 4K starting from SRAM_L2C_START so the bootblock starting address
+	* is fixed at SRAM_L2C_START + 4K, and the 4K can be reused after bootblock is started.
+	* To move the address, gen-bl-img.py also needs to be modified accordingly.
+	*/
+	BOOTBLOCK(0x02001000, 60K)
+	#endif
+
+	OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x0207D000, 272K)
+	PRERAM_CBFS_CACHE(0x020C1000, 48K)
+
+	CBFS_MCACHE(0x020CD000, 16K)
+	VBOOT2_WORK(0x020D1000, 12K)
+	FMAP_CACHE(0x020D4000, 2K)
+	TPM_LOG(0x020D4800, 2K)
+	TTB(0x020D5000, 28K)
+	DMA_COHERENT(0x020DC000, 4K)
+	STACK(0x020DD000, 15K)
+	TIMESTAMP(0x020E0C00, 1k)
+	PRERAM_CBMEM_CONSOLE(0x020E1000, 124K)
+	SRAM_L2C_END(0x02100000)
+
+	DRAM_START(0x40000000)
+	DRAM_DMA(0x40000000, 1M)
+	POSTRAM_CBFS_CACHE(0x40100000, 2M)
+	RAMSTAGE(0x40300000, 2M)
+
+	BL31(0x54600000, 0x60000)
+}
diff --git a/src/soc/mediatek/mt8189/include/soc/pll.h b/src/soc/mediatek/mt8189/include/soc/pll.h
new file mode 100644
index 0000000..3eb67bf
--- /dev/null
+++ b/src/soc/mediatek/mt8189/include/soc/pll.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * This file is created based on MT8189 Functional Specification
+ * Chapter number: 8.1
+ */
+
+#ifndef __SOC_MEDIATEK_MT8189_INCLUDE_SOC_PLL_H__
+#define __SOC_MEDIATEK_MT8189_INCLUDE_SOC_PLL_H__
+
+#include <soc/pll_common.h>
+
+/* top_div rate */
+enum {
+	CLK26M_HZ	= 26 * MHz,
+};
+
+/* top_mux rate */
+enum {
+	UART_HZ		= CLK26M_HZ,
+};
+
+#endif /* __SOC_MEDIATEK_MT8189_INCLUDE_SOC_PLL_H__ */
diff --git a/src/soc/mediatek/mt8189/include/soc/spi.h b/src/soc/mediatek/mt8189/include/soc/spi.h
new file mode 100644
index 0000000..f8978c8
--- /dev/null
+++ b/src/soc/mediatek/mt8189/include/soc/spi.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * This file is created based on MT8189 Functional Specification
+ * Chapter number: 9.17
+ */
+
+#ifndef __SOC_MEDIATEK_MT8189_INCLUDE_SOC_SPI_H__
+#define __SOC_MEDIATEK_MT8189_INCLUDE_SOC_SPI_H__
+
+#include <spi-generic.h>
+
+#endif /* __SOC_MEDIATEK_MT8189_INCLUDE_SOC_SPI_H__ */
diff --git a/src/soc/mediatek/mt8189/include/soc/timer.h b/src/soc/mediatek/mt8189/include/soc/timer.h
new file mode 100644
index 0000000..0c266eb
--- /dev/null
+++ b/src/soc/mediatek/mt8189/include/soc/timer.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * This file is created based on MT8189 Functional Specification
+ * Chapter number: 9.16
+ */
+
+#ifndef __SOC_MEDIATEK_MT8189_INCLUDE_SOC_TIMER_H__
+#define __SOC_MEDIATEK_MT8189_INCLUDE_SOC_TIMER_H__
+
+#include <soc/timer_v2.h>
+
+#endif /* __SOC_MEDIATEK_MT8189_INCLUDE_SOC_TIMER_H__ */
diff --git a/src/soc/mediatek/mt8189/soc.c b/src/soc/mediatek/mt8189/soc.c
new file mode 100644
index 0000000..3615c82
--- /dev/null
+++ b/src/soc/mediatek/mt8189/soc.c
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/device.h>
+#include <soc/emi.h>
+#include <symbols.h>
+
+static void soc_read_resources(struct device *dev)
+{
+	ram_range(dev, 0, (uintptr_t)_dram, sdram_size());
+}
+
+static void soc_init(struct device *dev)
+{
+}
+
+static struct device_operations soc_ops = {
+	.read_resources = soc_read_resources,
+	.set_resources = noop_set_resources,
+	.init = soc_init,
+};
+
+static void enable_soc_dev(struct device *dev)
+{
+	dev->ops = &soc_ops;
+}
+
+struct chip_operations soc_mediatek_mt8189_ops = {
+	.name = "SOC Mediatek MT8189",
+	.enable_dev = enable_soc_dev,
+};
diff --git a/src/soc/mediatek/mt8189/spi.c b/src/soc/mediatek/mt8189/spi.c
new file mode 100644
index 0000000..ae90bff
--- /dev/null
+++ b/src/soc/mediatek/mt8189/spi.c
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * This file is created based on MT8189 Functional Specification
+ * Chapter number: 9.17
+ */
+
+#include <device/mmio.h>
+#include <soc/addressmap.h>
+#include <soc/spi.h>
+
+static const struct spi_ctrlr spi_flash_ctrlr = {
+	.max_xfer_size = 65535,
+};
+
+const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = {
+	{
+		.ctrlr = &spi_flash_ctrlr,
+	},
+};
+
+const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map);
diff --git a/src/soc/mediatek/mt8189/timer.c b/src/soc/mediatek/mt8189/timer.c
new file mode 100644
index 0000000..2f299ea
--- /dev/null
+++ b/src/soc/mediatek/mt8189/timer.c
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * This file is created based on MT8189 Functional Specification
+ * Chapter number: 9.16
+ */
+
+#include <arch/lib_helpers.h>
+#include <commonlib/helpers.h>
+#include <delay.h>
+
+void init_timer(void)
+{
+	raw_write_cntfrq_el0(13 * MHz);
+}