Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83976?usp=email )
(
1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: Docs: Fix broken header references ......................................................................
Docs: Fix broken header references
MyST Parser automatically generates label "slugs" for headers which should be used to reference them from links [1]. These labels are in "slug-case", i.e. the original header text in lower case separated by dashes, with punctuation removed. This fixes a few "cross-reference target not found" warnings.
[1] https://myst-parser.readthedocs.io/en/latest/syntax/optional.html#anchor-slu...
Change-Id: Ia6970d03b961bde6d7cd0fa3297f8d84b75d3b34 Signed-off-by: Nicholas Chin nic.c3.14@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/83976 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Angel Pons th3fanbus@gmail.com --- M Documentation/mainboard/lenovo/Ivy_Bridge_series.md M Documentation/northbridge/intel/sandybridge/nri_freq.md M Documentation/releases/coreboot-4.13-relnotes.md M Documentation/superio/nuvoton/npcd378.md 4 files changed, 4 insertions(+), 4 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved
diff --git a/Documentation/mainboard/lenovo/Ivy_Bridge_series.md b/Documentation/mainboard/lenovo/Ivy_Bridge_series.md index 73d38fe..a7893e7 100644 --- a/Documentation/mainboard/lenovo/Ivy_Bridge_series.md +++ b/Documentation/mainboard/lenovo/Ivy_Bridge_series.md @@ -82,7 +82,7 @@ space for the `bios` region. This is usually referred to as *cleaning the ME* or *stripping the ME*. After reducing the Intel ME firmware size you must modify the original IFD, -[split the resulting coreboot ROM](#splitting-the-coreboot-rom) and then write +[split the resulting coreboot ROM](#splitting-the-corebootrom) and then write each ROM using an [external programmer]. Have a look at [me_cleaner] for more information.
diff --git a/Documentation/northbridge/intel/sandybridge/nri_freq.md b/Documentation/northbridge/intel/sandybridge/nri_freq.md index 45cac8d..0732870 100644 --- a/Documentation/northbridge/intel/sandybridge/nri_freq.md +++ b/Documentation/northbridge/intel/sandybridge/nri_freq.md @@ -160,7 +160,7 @@ slowest DIMMs' frequency will be selected, to prevent over-clocking it.
The selected frequency gives the PLL multiplier to operate at. In case the PLL -locks (see Take me to [Hard fuses](#hard_fuses)) the frequency will be used for +locks (see Take me to [Hard fuses](#hard-fuses)) the frequency will be used for all DIMMs. At this point it's not possible to change the multiplier again, until the system has been powered off. In case the PLL doesn't lock, the next smaller multiplier will be used until a working multiplier will be found. diff --git a/Documentation/releases/coreboot-4.13-relnotes.md b/Documentation/releases/coreboot-4.13-relnotes.md index 600bf67..29374d1 100644 --- a/Documentation/releases/coreboot-4.13-relnotes.md +++ b/Documentation/releases/coreboot-4.13-relnotes.md @@ -214,7 +214,7 @@
In order to minimize the usage of PCI bus mastering, the options we introduced in this release will be dropped in a future release again. For more details, please -see [Preparations to minimize enabling PCI bus mastering](#preparations-to-minimize-enabling-pci-bus-mastering-in-coreboot). +see [Preparations to minimize enabling PCI bus mastering](#preparations-to-minimize-enabling-pci-bus-mastering).
### Resource allocator v3
diff --git a/Documentation/superio/nuvoton/npcd378.md b/Documentation/superio/nuvoton/npcd378.md index 1cc081b..6e5bf66 100644 --- a/Documentation/superio/nuvoton/npcd378.md +++ b/Documentation/superio/nuvoton/npcd378.md @@ -78,7 +78,7 @@ ### LDN8
Custom HWM space. It exposes 256 byte of IO config space. -See [HWM](#HWM) for more details. +See [HWM](#hwm) for more details.
## HWM