Vladimir Serbinenko (phcoder@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5287
-gerrit
commit 9458c9eb84b06f375910361f453c1c1b2759a467 Author: Vladimir Serbinenko phcoder@gmail.com Date: Sun Feb 23 14:17:03 2014 +0100
NOTFORMERGE: x60gfx: step 13
Change-Id: I91c5619d7c2a212a55e301733374de8b23f8aa1f Signed-off-by: Vladimir Serbinenko phcoder@gmail.com --- src/drivers/intel/gma/edid.c | 20 +- src/drivers/intel/gma/i915_reg.h | 5 + src/mainboard/lenovo/x60/Kconfig | 1 + src/mainboard/lenovo/x60/Makefile.inc | 2 - src/mainboard/lenovo/x60/i915.c | 459 ++++--- src/mainboard/lenovo/x60/i915io.c | 2273 --------------------------------- src/northbridge/intel/i945/gma.c | 9 +- 7 files changed, 301 insertions(+), 2468 deletions(-)
diff --git a/src/drivers/intel/gma/edid.c b/src/drivers/intel/gma/edid.c index 0066b6a..15affd3 100644 --- a/src/drivers/intel/gma/edid.c +++ b/src/drivers/intel/gma/edid.c @@ -32,7 +32,7 @@ wait_rdy(u32 mmio) unsigned try = 100;
while (try--) { - if (read32(mmio + PCH_GMBUS2) & (1 << 11)) + if (read32(mmio + GMBUS2) & (1 << 11)) return; udelay(10); } @@ -45,29 +45,29 @@ intel_gmbus_read_edid(u32 mmio, u8 bus, u8 slave, u8 *edid)
wait_rdy(mmio); /* 100 KHz, hold 0ns, */ - write32(mmio + PCH_GMBUS0, bus); + write32(mmio + GMBUS0, bus); wait_rdy(mmio); /* Ensure index bits are disabled. */ - write32(mmio + PCH_GMBUS5, 0); - write32(mmio + PCH_GMBUS1, 0x46000000 | (slave << 1)); + write32(mmio + GMBUS5, 0); + write32(mmio + GMBUS1, 0x46000000 | (slave << 1)); wait_rdy(mmio); /* Ensure index bits are disabled. */ - write32(mmio + PCH_GMBUS5, 0); - write32(mmio + PCH_GMBUS1, 0x4a800001 | (slave << 1)); + write32(mmio + GMBUS5, 0); + write32(mmio + GMBUS1, 0x4a800001 | (slave << 1)); for (i = 0; i < 128 / 4; i++) { u32 reg32; wait_rdy(mmio); - reg32 = read32(mmio + PCH_GMBUS3); + reg32 = read32(mmio + GMBUS3); edid[4 * i] = reg32 & 0xff; edid[4 * i + 1] = (reg32 >> 8) & 0xff; edid[4 * i + 2] = (reg32 >> 16) & 0xff; edid[4 * i + 3] = (reg32 >> 24) & 0xff; } wait_rdy(mmio); - write32(mmio + PCH_GMBUS1, 0x4a800000 | (slave << 1)); + write32(mmio + GMBUS1, 0x4a800000 | (slave << 1)); wait_rdy(mmio); - write32(mmio + PCH_GMBUS0, 0x48000000); - write32(mmio + PCH_GMBUS2, 0x00008000); + write32(mmio + GMBUS0, 0x48000000); + write32(mmio + GMBUS2, 0x00008000);
printk (BIOS_INFO, "EDID:\n"); for (i = 0; i < 128; i++) { diff --git a/src/drivers/intel/gma/i915_reg.h b/src/drivers/intel/gma/i915_reg.h index 8c08d9f..9f134d0 100644 --- a/src/drivers/intel/gma/i915_reg.h +++ b/src/drivers/intel/gma/i915_reg.h @@ -959,6 +959,11 @@ #define DVOC_ON (1<<31) #define LVDS 0x61180 #define LVDS_ON (1<<31) +#define LVDS_CLOCK_A_POWERUP_ALL (3 << 8) +#define LVDS_CLOCK_B_POWERUP_ALL (3 << 4) +#define LVDS_CLOCK_BOTH_POWERUP_ALL (3 << 2) +#define LVDS_BORDER_ENABLE (1 << 15) +#define LVDS_PORT_ENABLE (1 << 31)
/* Scratch pad debug 0 reg: */ diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig index 7ed2665..977d9e5 100644 --- a/src/mainboard/lenovo/x60/Kconfig +++ b/src/mainboard/lenovo/x60/Kconfig @@ -26,6 +26,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_NATIVE_VGA_INIT select EARLY_CBMEM_INIT select H8_DOCK_EARLY_INIT + select INTEL_EDID
config MAINBOARD_DIR string diff --git a/src/mainboard/lenovo/x60/Makefile.inc b/src/mainboard/lenovo/x60/Makefile.inc index ecb7ce5..7ad57cd 100644 --- a/src/mainboard/lenovo/x60/Makefile.inc +++ b/src/mainboard/lenovo/x60/Makefile.inc @@ -21,5 +21,3 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += dock.c romstage-y += dock.c ramstage-y += dock.c ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += i915.c -ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += i915io.c -ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += intel_dp.c diff --git a/src/mainboard/lenovo/x60/i915.c b/src/mainboard/lenovo/x60/i915.c index 4870fd8..c215011 100644 --- a/src/mainboard/lenovo/x60/i915.c +++ b/src/mainboard/lenovo/x60/i915.c @@ -42,11 +42,17 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> #include <edid.h> -#include "i915io.h" - -enum { - vmsg = 1, vio = 2, vspin = 4, -}; +#include <drivers/intel/gma/edid.h> +#include <drivers/intel/gma/i915.h> + +#define LVDS_DETECTED (1 << 1) +#define LVDS_BORDER_ENABLE (1 << 15) +#define LVDS_PORT_ENABLE (1 << 31) +#define LVDS_CLOCK_A_POWERUP_ALL (3 << 8) +#define LVDS_CLOCK_B_POWERUP_ALL (3 << 4) +#define LVDS_CLOCK_BOTH_POWERUP_ALL (3 << 2) +#define DISPPLANE_BGRX888 (0x6<<26) +#define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
#define PGETLB_CTL 0x2020
@@ -62,18 +68,6 @@ static unsigned int physbase; #define PGETBL_ENABLED 0x00000001
-static u32 htotal, hblank, hsync, vtotal, vblank, vsync; - -const u8 x60_edid_data[] = { - 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x30, 0xae, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x0f, 0x01, 0x03, 0x80, 0x19, 0x12, 0x78, 0xea, 0xed, 0x75, 0x91, 0x57, 0x4f, 0x8b, 0x26, - 0x21, 0x50, 0x54, 0x21, 0x08, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, - 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x28, 0x15, 0x00, 0x40, 0x41, 0x00, 0x26, 0x30, 0x18, 0x88, - 0x36, 0x00, 0xf6, 0xb9, 0x00, 0x00, 0x00, 0x18, 0xed, 0x10, 0x00, 0x40, 0x41, 0x00, 0x26, 0x30, - 0x18, 0x88, 0x36, 0x00, 0xf6, 0xb9, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x61, - 0x43, 0x32, 0x61, 0x43, 0x28, 0x0f, 0x01, 0x00, 0x4c, 0xa3, 0x58, 0x4a, 0x00, 0x00, 0x00, 0xfe, - 0x00, 0x4c, 0x54, 0x4e, 0x31, 0x32, 0x31, 0x58, 0x4a, 0x2d, 0x4c, 0x30, 0x37, 0x0a, 0x00, 0x00, -}; #define READ32(addr) io_i915_READ32(addr) #define WRITE32(val, addr) io_i915_WRITE32(val, addr)
@@ -84,7 +78,7 @@ static char *regname(unsigned long addr) return name; }
-unsigned long io_i915_READ32(unsigned long addr) +static unsigned long io_i915_READ32(unsigned long addr) { unsigned long val; outl(addr, addrport); @@ -94,41 +88,6 @@ unsigned long io_i915_READ32(unsigned long addr) return val; }
-void io_i915_WRITE32(unsigned long val, unsigned long addr) -{ - if (verbose & vio) - printk(BIOS_SPEW, "%s: outl %08lx\n", regname(addr), val); - outl(addr, addrport); - outl(val, dataport); -} - - -/* - 2560 - 4 words per - 4 *p - 10240 - 4k bytes per page - 4096/p - 2.50 - 1700 lines - 1700 * p - 4250.00 - PTEs -*/ -static void -setgtt(int start, int end, unsigned long base, int inc) -{ - int i; - - printk(BIOS_INFO, "%s(%d,%d,0x%08lx,%d);\n", - __func__, start, end, base, inc); - - for (i = start; i < end; i++) { - u32 word = base + i*inc; - WRITE32(word|1, (i*4)|1); - } -}
int gtt_setup(unsigned int mmiobase); int gtt_setup(unsigned int mmiobase) @@ -174,114 +133,27 @@ static unsigned long globalmicroseconds(void) return microseconds(globalstart, rdtscll()); }
-extern struct iodef iodefs[]; -extern int niodefs; - -/* fill the palette. This runs when the P opcode is hit. */ -static void palette(void) -{ - int i; - unsigned long color = 0; - - for (i = 0; i < 256; i++, color += 0x010101) - io_i915_WRITE32(color, _LGC_PALETTE_A + (i<<2)); -} - -static unsigned long times[4096]; - -static int run(int index) -{ - int i, prev = 0; - struct iodef *id, *lastidread = 0; - unsigned long u, t; - if (index >= niodefs) - return index; - /* state machine! */ - for (i = index, id = &iodefs[i]; id->op; i++, id++) { - switch (id->op) { - case M: - if (verbose & vmsg) - printk(BIOS_SPEW, "%ld: %s\n", - globalmicroseconds(), id->msg); - break; - case P: - palette(); - break; - case R: - u = READ32(id->addr); - if (verbose & vio) - printk(BIOS_SPEW, "\texpect %08lx\n", id->data); - /* we're looking for something. */ - if (lastidread->addr == id->addr) { - /* they're going to be polling. - * just do it 1000 times - */ - for (t = 0; t < 1000 && id->data != u; t++) - u = READ32(id->addr); - - if (verbose & vspin) - printk(BIOS_SPEW, - "%s: # loops %ld got %08lx want %08lx\n", - regname(id->addr), - t, u, id->data); - } - lastidread = id; - break; - case W: - WRITE32(id->data, id->addr); - if (id->addr == PCH_PP_CONTROL) { - if (verbose & vio) - printk(BIOS_SPEW, "PCH_PP_CONTROL\n"); - switch (id->data & 0xf) { - case 8: - break; - case 7: - break; - default: - udelay(100000); - if (verbose & vio) - printk(BIOS_SPEW, "U %d\n", - 100000); - } - } - break; - case V: - if (id->count < 8) { - prev = verbose; - verbose = id->count; - } else { - verbose = prev; - } - printk(BIOS_SPEW, "Change verbosity to %d\n", verbose); - break; - case I: - printk(BIOS_SPEW, "run: return %d\n", i+1); - return i+1; - break; - default: - printk(BIOS_SPEW, "BAD TABLE, opcode %d @ %d\n", - id->op, i); - return -1; - } - if (id->udelay) - udelay(id->udelay); - if (i < ARRAY_SIZE(times)) - times[i] = globalmicroseconds(); - } - printk(BIOS_SPEW, "run: return %d\n", i); - return i+1; -} - int i915lightup(unsigned int physbase, unsigned int iobase, unsigned int mmio, unsigned int gfx);
int i915lightup(unsigned int pphysbase, unsigned int piobase, unsigned int pmmio, unsigned int pgfx) { - static struct edid edid; - - int index; + struct edid edid; + u8 x60_edid_data[256]; unsigned long temp; + int hpolarity, vpolarity; + u32 candp1, candn; + u32 best_delta = 0xffffffff; + u32 target_frequency; + u32 pixel_p1 = 1; + u32 pixel_n = 1; + u32 pixel_m1 = 1; + u32 pixel_m2 = 1; + u32 hactive, vactive, right_border, bottom_border; + u32 vsync, hsync, vblank, hblank, hfront_porch, vfront_porch; + u32 i, j; + mmio = (void *)pmmio; addrport = piobase; dataport = addrport + 4; @@ -292,34 +164,258 @@ int i915lightup(unsigned int pphysbase, unsigned int piobase, (void *)graphics, mmio, addrport, physbase); globalstart = rdtscll();
- - decode_edid((unsigned char *)&x60_edid_data, + intel_gmbus_read_edid(pmmio, 3, 0x50, x60_edid_data); + decode_edid(x60_edid_data, sizeof(x60_edid_data), &edid);
- htotal = (edid.ha - 1) | ((edid.ha + edid.hbl - 1) << 16); - printk(BIOS_SPEW, "I915_WRITE(HTOTAL(pipe), %08x)\n", htotal); - - hblank = (edid.ha - 1) | ((edid.ha + edid.hbl - 1) << 16); - printk(BIOS_SPEW, "I915_WRITE(HBLANK(pipe),0x%08x)\n", hblank); - - hsync = (edid.ha + edid.hso - 1) | - ((edid.ha + edid.hso + edid.hspw - 1) << 16); - printk(BIOS_SPEW, "I915_WRITE(HSYNC(pipe),0x%08x)\n", hsync); - - vtotal = (edid.va - 1) | ((edid.va + edid.vbl - 1) << 16); - printk(BIOS_SPEW, "I915_WRITE(VTOTAL(pipe), %08x)\n", vtotal); + hpolarity = (edid.phsync == '-'); + vpolarity = (edid.pvsync == '-'); + hactive = edid.x_resolution; + vactive = edid.y_resolution; + right_border = edid.hborder; + bottom_border = edid.vborder; + vblank = edid.vbl; + hblank = edid.hbl; + vsync = edid.vspw; + hsync = edid.hspw; + hfront_porch = edid.hso; + vfront_porch = edid.vso; + + for (i = 0; i < 2; i++) + for (j = 0; j < 0x100; j++) + write32(pmmio + PALETTE(i) + 4 * j, 0x10101 * j); + +#define IS_DUAL_CHANNEL 0 +#define USE_SSC 1 + + read32(pmmio+PP_ON_DELAYS); // 0x00000000 // replay + read32(pmmio+PP_OFF_DELAYS); // 0x00000000 // replay + write32(pmmio+PP_ON_DELAYS,0x00000000); // replay + write32(pmmio+PP_OFF_DELAYS,0x00000000); // replay + write32(pmmio+INSTPM+0x24, MI_ARB_C3_LP_WRITE_ENABLE | 0x08000800); // replay + write32(pmmio+RENDER_RING_BASE,0x00000000); // replay + write32(pmmio+RENDER_RING_BASE+0x4,0x00000000); // replay + write32(pmmio+RENDER_RING_BASE+0x8,0x00000000); // replay + write32(pmmio+RENDER_RING_BASE+0xc,0x00000000); // replay + write32(pmmio+RENDER_RING_BASE+0x10,0x00000000); // replay + write32(pmmio+RENDER_RING_BASE+0x14,0x00000000); // replay + write32(pmmio+RENDER_RING_BASE+0x18,0x00000000); // replay + write32(pmmio+RENDER_RING_BASE+0x1c,0x00000000); // replay + write32(pmmio+FENCE_REG_965_0,0x00000000); // replay + write32(pmmio+FENCE_REG_965_0+0x4,0x00000000); // replay + write32(pmmio+FENCE_REG_965_0+0x8,0x00000000); // replay + write32(pmmio+FENCE_REG_965_0+0xc,0x00000000); // replay + write32(pmmio+FENCE_REG_965_0+0x10,0x00000000); // replay + write32(pmmio+FENCE_REG_965_0+0x14,0x00000000); // replay + write32(pmmio+FENCE_REG_965_0+0x18,0x00000000); // replay + write32(pmmio+FENCE_REG_965_0+0x1c,0x00000000); // replay + write32(pmmio+VGACNTRL, VGA_DISP_DISABLE | 0x80000000); // replay + read32(pmmio+PFIT_CONTROL); // 0x00000000 // replay + read32(pmmio+PP_CONTROL); // 0x00000000 // replay + mdelay(1); + write32(pmmio+PP_CONTROL,0xabcd0000); // replay + mdelay(1); + read32(pmmio+BLC_PWM_CTL); // 0x00000000 // replay + read32(pmmio+DVOB); // 0x00300000 // replay + read32(pmmio+DVOC); // 0x00300000 // replay + write32(pmmio+HWS_PGA,0x352d2000); // replay + write32(pmmio+PRB0_CTL,0x00000000); // replay + write32(pmmio+PRB0_HEAD,0x00000000); // replay + write32(pmmio+PRB0_TAIL,0x00000000); // replay + read32(pmmio+PRB0_HEAD); // 0x00000000 // replay + write32(pmmio+PRB0_START,0x00000000); // replay + write32(pmmio+PRB0_CTL,0x0001f001); // replay + read32(pmmio+PRB0_CTL); // 0x0001f001 // replay + read32(pmmio+PRB0_START); // 0x00000000 // replay + read32(pmmio+PRB0_HEAD); // 0x00000000 // replay + read32(pmmio+PRB0_TAIL); // 0x00000000 // replay + read32(pmmio+0x6104); // 0x00000000 // replay + write32(pmmio+0x6104,0x0000000b); // replay + write32(pmmio+ECOSKPD,0x00010000); // replay + read32(pmmio+_PIPEBCONF); // 0x00000000 // replay + read32(pmmio+LVDS); // 0x40000000 // replay + read32(pmmio+_FDI_TXB_CTL); // 0x00000000 // replay + write32(pmmio+_PIPEBCONF,0x00000000); // replay + write32(pmmio+PORT_HOTPLUG_EN,0x00000000); // replay + read32(pmmio+PORT_HOTPLUG_STAT); // 0x00000000 // replay + write32(pmmio+PORT_HOTPLUG_STAT,0x00000000); // replay + write32(pmmio+HWSTAM,0x0000effe); // replay + write32(pmmio+_PIPEASTAT,0x00000000); // replay + write32(pmmio+_PIPEBSTAT,0x00000000); // replay + read32(pmmio+PORT_HOTPLUG_EN); // 0x00000000 // replay + write32(pmmio+PORT_HOTPLUG_EN, CRT_HOTPLUG_INT_EN | CRT_HOTPLUG_VOLTAGE_COMPARE_50 | 0x00000220); // replay + read32(pmmio+PORT_HOTPLUG_EN); // CRT_HOTPLUG_INT_EN | CRT_HOTPLUG_VOLTAGE_COMPARE_50 | 0x00000220 // replay + write32(pmmio+PORT_HOTPLUG_EN, CRT_HOTPLUG_INT_EN | CRT_HOTPLUG_FORCE_DETECT | CRT_HOTPLUG_VOLTAGE_COMPARE_50 | 0x00000228); // replay + read32(pmmio+PORT_HOTPLUG_EN); // CRT_HOTPLUG_INT_EN | CRT_HOTPLUG_FORCE_DETECT | CRT_HOTPLUG_VOLTAGE_COMPARE_50 | 0x00000228 // replay + read32(pmmio+PORT_HOTPLUG_EN); // CRT_HOTPLUG_INT_EN | CRT_HOTPLUG_VOLTAGE_COMPARE_50 | 0x00000220 // replay + read32(pmmio+PORT_HOTPLUG_STAT); // 0x00000000 // replay + write32(pmmio+PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS | 0x00000800); // replay + write32(pmmio+PORT_HOTPLUG_EN, CRT_HOTPLUG_INT_EN | CRT_HOTPLUG_VOLTAGE_COMPARE_50 | 0x00000220); // replay + write32(pmmio+_DSPBADDR,0x00020000); // replay + read32(pmmio+DSPARB); // (DSPARB_CSTART_SHIFT & 0x4) | 0x00001d9c // replay + write32(pmmio+FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0x80000000); // replay + write32(pmmio+FW_BLC,0x011d011a); // replay + write32(pmmio+FW_BLC2,0x00000102); // replay + read32(pmmio+DSPARB); // (DSPARB_CSTART_SHIFT & 0x4) | 0x00001d9c // replay + write32(pmmio+FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0x80000000); // replay + write32(pmmio+FW_BLC_SELF,0x0001002f); // replay + write32(pmmio+FW_BLC,0x0101011a); // replay + write32(pmmio+FW_BLC2,0x00000102); // replay + write32(pmmio+FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0x80008000); // replay + write32(pmmio+_DSPBCNTR,0xd8000000); // replay + read32(pmmio+_DSPBADDR); // 0x00020000 // replay + write32(pmmio+_DSPBADDR,0x00020000); // replay + write32(pmmio+INSTPM,0x08000800); // replay + write32(pmmio+FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0x80000000); // replay + write32(pmmio+FW_BLC,0x011d011a); // replay + write32(pmmio+FW_BLC2,0x00000102); // replay + + target_frequency = IS_DUAL_CHANNEL ? edid.pixel_clock + : (2 * edid.pixel_clock); + + /* Find suitable divisors. */ + for (candp1 = 1; candp1 <= 8; candp1++) { + for (candn = 5; candn <= 10; candn++) { + u32 cur_frequency; + u32 m; /* 77 - 131. */ + u32 denom; /* 35 - 560. */ + u32 current_delta; + + denom = candn * candp1 * 7; + /* Doesnt overflow for up to + 5000000 kHz = 5 GHz. */ + m = (target_frequency * denom + 60000) / 120000; + + if (m < 77 || m > 131) + continue; + + cur_frequency = (120000 * m) / denom; + if (target_frequency > cur_frequency) + current_delta = target_frequency - cur_frequency; + else + current_delta = cur_frequency - target_frequency; + + + if (best_delta > current_delta) { + best_delta = current_delta; + pixel_n = candn; + pixel_p1 = candp1; + pixel_m2 = ((m + 3) % 5) + 7; + pixel_m1 = (m - pixel_m2) / 5; + } + } + }
- vblank = (edid.va - 1) | ((edid.va + edid.vbl - 1) << 16); - printk(BIOS_SPEW, "I915_WRITE(VBLANK(pipe),0x%08x)\n", vblank); + if (best_delta == 0xffffffff) { + printk (BIOS_ERR, "Couldn't find GFX clock divisors\n"); + return -1; + }
- vsync = (edid.va + edid.vso - 1) | - ((edid.va + edid.vso + edid.vspw - 1) << 16); - printk(BIOS_SPEW, "I915_WRITE(VSYNC(pipe),0x%08x)\n", vsync); + write32(pmmio + DSPCNTR(0), DISPPLANE_BGRX888 + | DISPPLANE_SEL_PIPE_B | DISPPLANE_GAMMA_ENABLE); + + mdelay(1); + write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS + | (read32(pmmio + PP_CONTROL) & ~PANEL_UNLOCK_MASK)); + write32(pmmio + FP0(1), + ((pixel_n - 2) << 16) + | ((pixel_m1 - 2) << 8) | pixel_m2); + write32(pmmio + DPLL(1), + DPLL_VCO_ENABLE | DPLLB_MODE_LVDS + | (IS_DUAL_CHANNEL ? DPLLB_LVDS_P2_CLOCK_DIV_7 + : DPLLB_LVDS_P2_CLOCK_DIV_14) + | (0x10000 << (pixel_p1 - 1)) + | ((USE_SSC ? 3 : 0) << 13) + | (0x1 << (pixel_p1 - 1))); + mdelay(1); + write32(pmmio + DPLL(1), + DPLL_VCO_ENABLE | DPLLB_MODE_LVDS + | (IS_DUAL_CHANNEL ? DPLLB_LVDS_P2_CLOCK_DIV_7 + : DPLLB_LVDS_P2_CLOCK_DIV_14) + | (0x10000 << (pixel_p1 - 1)) + | ((USE_SSC ? 3 : 0) << 13) + | (0x1 << (pixel_p1 - 1))); + mdelay(1); + write32(pmmio + HTOTAL(1), + ((hactive + right_border + hblank - 1) << 16) + | (hactive - 1)); + write32(pmmio + HBLANK(1), + ((hactive + right_border + hblank - 1) << 16) + | (hactive + right_border - 1)); + write32(pmmio + HSYNC(1), + ((hactive + right_border + hfront_porch + hsync - 1) << 16) + | (hactive + right_border + hfront_porch - 1)); + + write32(pmmio + VTOTAL(1), ((vactive + bottom_border + vblank - 1) << 16) + | (vactive - 1)); + write32(pmmio + VBLANK(1), ((vactive + bottom_border + vblank - 1) << 16) + | (vactive + bottom_border - 1)); + write32(pmmio + VSYNC(1), + (vactive + bottom_border + vfront_porch + vsync - 1) + | (vactive + bottom_border + vfront_porch - 1)); + + write32(pmmio + PIPESRC(1), ((hactive - 1) << 16) | (vactive - 1)); + write32(pmmio + PF_CTL(0),0); + write32(pmmio + PF_WIN_SZ(0), 0); + write32(pmmio + PF_WIN_POS(0), 0); + + mdelay(1); + + write32(pmmio+DSPSIZE(0),(hactive - 1) | ((vactive - 1) << 16)); + write32(pmmio+DSPPOS(0),0); + + write32(pmmio+FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0x80000000); // replay + write32(pmmio+FW_BLC,0x011d011a); // replay + write32(pmmio+FW_BLC2,0x00000102); // replay + write32(pmmio+FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0x80000000); // replay + write32(pmmio+FW_BLC_SELF,0x0001003f); // replay + write32(pmmio+FW_BLC,0x011d0109); // replay + write32(pmmio+FW_BLC2,0x00000102); // replay + write32(pmmio+FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0x80008000); // replay + write32(pmmio+PFIT_PGM_RATIOS,0x00000000); // replay + write32(pmmio+PFIT_CONTROL,(PFIT_PIPE_SHIFT & 0x8) | 0x00000008); // replay + read32(pmmio+BLC_PWM_CTL); // 0x00000000 // replay + write32(pmmio+BLC_PWM_CTL,0x00000002); // replay + + + edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; + write32(pmmio + DSPADDR(0), 0x20000); + write32(pmmio + DSPSURF(0), 0); + write32(pmmio + DSPSTRIDE(0), edid.bytes_per_line); + write32(pmmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888 + | DISPPLANE_SEL_PIPE_B | DISPPLANE_GAMMA_ENABLE); + mdelay(1); + + write32(pmmio + PIPECONF(1), (1 << 31)); + write32(pmmio + LVDS, + LVDS_PORT_ENABLE + | (hpolarity << 20) | (vpolarity << 21) + | (IS_DUAL_CHANNEL ? LVDS_CLOCK_B_POWERUP_ALL + | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) + | LVDS_CLOCK_A_POWERUP_ALL | (1 << 30)); + + write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_OFF); + write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_RESET); + mdelay(1); + write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS + | PANEL_POWER_ON | PANEL_POWER_RESET); + + printk (BIOS_DEBUG, "waiting for panel powerup\n"); + while (1) { + u32 reg32; + reg32 = read32(pmmio + PP_STATUS); + if (((reg32 >> 28) & 3) == 0) + break; + } + printk (BIOS_DEBUG, "panel powered up\n");
- printk(BIOS_SPEW, "Table has %d elements\n", niodefs); + write32(pmmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET);
- index = run(0); - printk(BIOS_SPEW, "Run returns %d\n", index); + /* Clear interrupts. */ + write32(pmmio + DEIIR, 0xffffffff); + write32(pmmio + SDEIIR, 0xffffffff); + write32(pmmio + IIR, 0xffffffff); + write32(pmmio + IMR, 0xffffffff);
verbose = 0; /* GTT is the Global Translation Table for the graphics pipeline. @@ -351,7 +447,12 @@ int i915lightup(unsigned int pphysbase, unsigned int piobase, return 0; }
- setgtt(0, 800 , physbase, 4096); + /* Setup GTT. */ + for (i = 0; i < 0x2000; i++) + { + outl((i << 2) | 1, piobase); + outl(physbase + (i << 12) + 1, piobase + 4); + }
temp = READ32(PGETLB_CTL); printk(BIOS_INFO, "GTT PGETLB_CTL register: 0x%lx\n", temp); @@ -362,8 +463,8 @@ int i915lightup(unsigned int pphysbase, unsigned int piobase, printk(BIOS_ERR, "ERROR: GTT is still Disabled!!!\n");
printk(BIOS_SPEW, "memset %p to 0x00 for %d bytes\n", - (void *)graphics, FRAME_BUFFER_BYTES); - memset((void *)graphics, 0x00, FRAME_BUFFER_BYTES); + (void *)graphics, hactive * vactive * 4); + memset((void *)graphics, 0x00, hactive * vactive * 4);
printk(BIOS_SPEW, "%ld microseconds\n", globalmicroseconds());
diff --git a/src/mainboard/lenovo/x60/i915io.c b/src/mainboard/lenovo/x60/i915io.c deleted file mode 100644 index 3552867..0000000 --- a/src/mainboard/lenovo/x60/i915io.c +++ /dev/null @@ -1,2273 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <stdint.h> -#include "i915io.h" - -struct iodef iodefs[] = { -{V, 0,}, -{M, 1, "Linux agpgart interface v0.103", 0x0, 0x0, 0}, -{M, 1, "agpgart-intel 0000:00:00.0:Intel 945GM Chipset", 0x0, 0x0, 0}, -{M, 1, "agpgart-intel 0000:00:00.0:detected gtt size:262144K total, 262144K mappable", 0x0, 0x0, 0}, -{M, 1, "agpgart-intel 0000:00:00.0:detected 8192K stolen memory", 0x0, 0x0, 0}, -{M, 1, "agpgart-intel 0000:00:00.0:AGP aperture is 256M @ 0xd0000000", 0x0, 0x0, 0}, -{M, 1, "[drm] Initialized drm 1.1.0 20060810", 0x0, 0x0, 0}, -{M, 1, "[drm] radeon defaulting to kernel modesetting.", 0x0, 0x0, 0}, -{M, 1, "[drm] radeon kernel modesetting enabled.", 0x0, 0x0, 0}, -{M, 1, "i915 0000:00:02.0:setting latency timer to 64", 0x0, 0x0, 0}, -{W, 1, "", 0x5100, 0x00000000, 0}, -{R, 1, "", PP_ON_DELAYS, 0x00000000, 0}, -{R, 1, "", PP_OFF_DELAYS, 0x00000000, 0}, -{W, 1, "", PP_ON_DELAYS, 0x00000000, 0}, -{W, 1, "", PP_OFF_DELAYS, 0x00000000, 0}, -{W, 1, "", INSTPM+0x24, MI_ARB_C3_LP_WRITE_ENABLE | 0x08000800, 0}, -{W, 1, "", RENDER_RING_BASE, 0x00000000, 0}, -{W, 1, "", RENDER_RING_BASE+0x4, 0x00000000, 0}, -{W, 1, "", RENDER_RING_BASE+0x8, 0x00000000, 0}, -{W, 1, "", RENDER_RING_BASE+0xc, 0x00000000, 0}, -{W, 1, "", RENDER_RING_BASE+0x10, 0x00000000, 0}, -{W, 1, "", RENDER_RING_BASE+0x14, 0x00000000, 0}, -{W, 1, "", RENDER_RING_BASE+0x18, 0x00000000, 0}, -{W, 1, "", RENDER_RING_BASE+0x1c, 0x00000000, 0}, -{W, 1, "", FENCE_REG_965_0, 0x00000000, 0}, -{W, 1, "", FENCE_REG_965_0+0x4, 0x00000000, 0}, -{W, 1, "", FENCE_REG_965_0+0x8, 0x00000000, 0}, -{W, 1, "", FENCE_REG_965_0+0xc, 0x00000000, 0}, -{W, 1, "", FENCE_REG_965_0+0x10, 0x00000000, 0}, -{W, 1, "", FENCE_REG_965_0+0x14, 0x00000000, 0}, -{W, 1, "", FENCE_REG_965_0+0x18, 0x00000000, 0}, -{W, 1, "", FENCE_REG_965_0+0x1c, 0x00000000, 0}, -{R, 1, "", DCC, DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED | DCC_CHANNEL_XOR_BIT_17 | 0x000f0202, 0}, -{M, 1, "[drm] Supports vblank timestamp caching Rev 1 (10.10.2010).", 0x0, 0x0, 0}, -{M, 1, "[drm] Driver supports precise vblank timestamp query.", 0x0, 0x0, 0}, -{M, 1, "i915 0000:00:02.0:Invalid ROM contents", 0x0, 0x0, 0}, -{M, 1, "[drm] failed to find VBIOS tables", 0x0, 0x0, 0}, -{M, 1, "vgaarb:device changed decodes:PCI:0000:00:02.0,olddecodes=io+mem,decodes=io+mem:owns=io+mem", 0x0, 0x0, 0}, -{W, 1, "", VGACNTRL, VGA_DISP_DISABLE | 0x80000000, 0}, -{R, 1, "", PFIT_CONTROL, 0x00000000, 0}, -{W, 1, "", 0x5100, 0x00000003, 0}, -{W, 1, "", 0x5104, 0x460100a1, 0}, -{R, 1, "", 0x5108, 0x00004a00, 0}, -{R, 1, "", 0x510c, 0x00000000, 0}, -{R, 1, "", 0x5108, 0x0000c200, 0}, -{W, 1, "", 0x5104, 0x48000000, 0}, -{R, 1, "", 0x5108, 0x00008800, 0}, -{W, 1, "", 0x5100, 0x00000000, 0}, -{W, 1, "", 0x5100, 0x00000003, 0}, -{W, 1, "", 0x5104, 0x468000a1, 0}, -{R, 1, "", 0x5108, 0x00008a08, 0}, -{R, 1, "", 0x510c, 0xffffff00, 0}, -{R, 1, "", 0x5108, 0x00008a0c, 0}, -{R, 1, "", 0x510c, 0x00ffffff, 0}, -{R, 1, "", 0x5108, 0x00008a10, 0}, -{R, 1, "", 0x510c, 0x4000ae30, 0}, -{R, 1, "", 0x5108, 0x00008a14, 0}, -{R, 1, "", 0x510c, 0x00000000, 0}, -{R, 1, "", 0x5108, 0x00008a18, 0}, -{R, 1, "", 0x510c, 0x03010f00, 0}, -{R, 1, "", 0x5108, 0x00008a1c, 0}, -{R, 1, "", 0x510c, 0x78121980, 0}, -{R, 1, "", 0x5108, 0x00008a20, 0}, -{R, 1, "", 0x510c, 0x9175edea, 0}, -{R, 1, "", 0x5108, 0x00008a24, 0}, -{R, 1, "", 0x510c, 0x268b4f57, 0}, -{R, 1, "", 0x5108, 0x00008a28, 0}, -{R, 1, "", 0x510c, 0x21545021, 0}, -{R, 1, "", 0x5108, 0x00008a2c, 0}, -{R, 1, "", 0x510c, 0x01010008, 0}, -{R, 1, "", 0x5108, 0x00008a30, 0}, -{R, 1, "", 0x510c, 0x01010101, 0}, -{R, 1, "", 0x5108, 0x00008a34, 0}, -{R, 1, "", 0x510c, 0x01010101, 0}, -{R, 1, "", 0x5108, 0x00008a38, 0}, -{R, 1, "", 0x510c, 0x01010101, 0}, -{R, 1, "", 0x5108, 0x00008a3c, 0}, -{R, 1, "", 0x510c, 0x15280101, 0}, -{R, 1, "", 0x5108, 0x00008a40, 0}, -{R, 1, "", 0x510c, 0x00414000, 0}, -{R, 1, "", 0x5108, 0x00008a44, 0}, -{R, 1, "", 0x510c, 0x88183026, 0}, -{R, 1, "", 0x5108, 0x00008a48, 0}, -{R, 1, "", 0x510c, 0xb9f60036, 0}, -{R, 1, "", 0x5108, 0x00008a4c, 0}, -{R, 1, "", 0x510c, 0x18000000, 0}, -{R, 1, "", 0x5108, 0x00008a50, 0}, -{R, 1, "", 0x510c, 0x400010ed, 0}, -{R, 1, "", 0x5108, 0x00008a54, 0}, -{R, 1, "", 0x510c, 0x30260041, 0}, -{R, 1, "", 0x5108, 0x00008a58, 0}, -{R, 1, "", 0x510c, 0x00368818, 0}, -{R, 1, "", 0x5108, 0x00008a5c, 0}, -{R, 1, "", 0x510c, 0x0000b9f6, 0}, -{R, 1, "", 0x5108, 0x00008a60, 0}, -{R, 1, "", 0x510c, 0x00001800, 0}, -{R, 1, "", 0x5108, 0x00008a64, 0}, -{R, 1, "", 0x510c, 0x61000f00, 0}, -{R, 1, "", 0x5108, 0x00008a68, 0}, -{R, 1, "", 0x510c, 0x43613243, 0}, -{R, 1, "", 0x5108, 0x00008a6c, 0}, -{R, 1, "", 0x510c, 0x00010f28, 0}, -{R, 1, "", 0x5108, 0x00008a70, 0}, -{R, 1, "", 0x510c, 0x4a58a34c, 0}, -{R, 1, "", 0x5108, 0x00008a74, 0}, -{R, 1, "", 0x510c, 0xfe000000, 0}, -{R, 1, "", 0x5108, 0x00008a78, 0}, -{R, 1, "", 0x510c, 0x4e544c00, 0}, -{R, 1, "", 0x5108, 0x00008a7c, 0}, -{R, 1, "", 0x510c, 0x58313231, 0}, -{R, 1, "", 0x5108, 0x0000ca00, 0}, -{R, 1, "", 0x510c, 0x304c2d4a, 0}, -{R, 1, "", 0x5108, 0x0000ca00, 0}, -{R, 1, "", 0x510c, 0x00000a37, 0}, -{R, 1, "", 0x5108, 0x0000c200, 0}, -{W, 1, "", 0x5104, 0x48000000, 0}, -{R, 1, "", 0x5108, 0x00008800, 0}, -{W, 1, "", 0x5100, 0x00000000, 0}, -{R, 1, "", PP_CONTROL, 0x00000000, 0}, -{W, 1, "", PP_CONTROL, 0xabcd0000, 0}, -{R, 2, "", BLC_PWM_CTL, 0x00000000, 0}, -{R, 2, "", DVOB, 0x00300000, 0}, -{R, 1, "", DVOC, 0x00300000, 0}, -{R, 1, "", TV_CTL, 0x00000000, 0}, -{R, 1, "", TV_DAC, 0x00000000, 0}, -{W, 1, "", TV_DAC, 0x08000000, 0}, -{R, 1, "", TV_DAC, 0x08000000, 0}, -{W, 1, "", TV_DAC, 0x00000000, 0}, -{R, 1, "", TV_DAC, 0x00000000, 0}, -{W, 1, "", TV_DAC, 0x00000000, 0}, -{M, 1, "tsc:Refined TSC clocksource calibration:1662.499 MHz", 0x0, 0x0, 0}, -{W, 1, "", HWS_PGA, 0x352d2000, 0}, -{W, 1, "", PRB0_CTL, 0x00000000, 0}, -{M, 1, "Switching to clocksource tsc", 0x0, 0x0, 0}, -{W, 1, "", PRB0_HEAD, 0x00000000, 0}, -{W, 1, "", PRB0_TAIL, 0x00000000, 0}, -{R, 1, "", PRB0_HEAD, 0x00000000, 0}, -{W, 1, "", PRB0_START, 0x00000000, 0}, -{W, 1, "", PRB0_CTL, 0x0001f001, 0}, -{R, 1, "", PRB0_CTL, 0x0001f001, 0}, -{R, 1, "", PRB0_START, 0x00000000, 0}, -{R, 2, "", PRB0_HEAD, 0x00000000, 0}, -{R, 1, "", PRB0_TAIL, 0x00000000, 0}, -{R, 1, "", 0x6104, 0x00000000, 0}, -{W, 1, "", 0x6104, 0x0000000b, 0}, -{W, 1, "", ECOSKPD, 0x00010000, 0}, -{M, 1, "[drm] initialized overlay support", 0x0, 0x0, 0}, -{R, 1, "", _PIPEACONF, 0x00000000, 0}, -{R, 1, "", _PIPEBCONF, 0x00000000, 0}, -{R, 1, "", LVDS, 0x40000000, 0}, -{R, 1, "", _FDI_TXB_CTL, 0x00000000, 0}, -{R, 1, "", TV_CTL, 0x00000000, 0}, -{R, 1, "", LVDS, 0x40000000, 0}, -{R, 1, "", _FDI_TXB_CTL, 0x00000000, 0}, -{R, 1, "", TV_CTL, 0x00000000, 0}, -{R, 1, "", _PIPEACONF, 0x00000000, 0}, -{W, 1, "", _PIPEACONF, 0x00000000, 0}, -{R, 1, "", _DSPACNTR, 0x00000000, 0}, -{R, 1, "", _PIPEBCONF, 0x00000000, 0}, -{W, 1, "", _PIPEBCONF, 0x00000000, 0}, -{R, 1, "", _DSPBCNTR, 0x00000000, 0}, -{R, 1, "", LVDS, 0x40000000, 0}, -{R, 1, "", _FDI_TXB_CTL, 0x00000000, 0}, -{R, 1, "", TV_CTL, 0x00000000, 0}, -{R, 1, "", LVDS, 0x40000000, 0}, -{R, 1, "", _FDI_TXB_CTL, 0x00000000, 0}, -{R, 1, "", TV_CTL, 0x00000000, 0}, -{R, 1, "", _PIPEACONF, 0x00000000, 0}, -{R, 1, "", _PIPEBCONF, 0x00000000, 0}, -{W, 1, "", PORT_HOTPLUG_EN, 0x00000000, 0}, -{R, 1, "", PORT_HOTPLUG_STAT, 0x00000000, 0}, -{W, 1, "", PORT_HOTPLUG_STAT, 0x00000000, 0}, -{W, 1, "", HWSTAM, 0x0000effe, 0}, -{W, 1, "", _PIPEASTAT, 0x00000000, 0}, -{W, 1, "", _PIPEBSTAT, 0x00000000, 0}, -{W, 1, "", IMR, 0xffffffff, 0}, -{W, 1, "", IER, 0x00000000, 0}, -{W, 1, "", EMR, 0xffffffed, 0}, -{W, 1, "", IMR, 0xfffd73ae, 0}, -{W, 1, "", IER, 0x00028053, 0}, -{R, 1, "", PORT_HOTPLUG_EN, 0x00000000, 0}, -{W, 1, "", PORT_HOTPLUG_EN, CRT_HOTPLUG_INT_EN | CRT_HOTPLUG_VOLTAGE_COMPARE_50 | 0x00000220, 0}, -{R, 1, "", PORT_HOTPLUG_EN, CRT_HOTPLUG_INT_EN | CRT_HOTPLUG_VOLTAGE_COMPARE_50 | 0x00000220, 0}, -{W, 1, "", PORT_HOTPLUG_EN, CRT_HOTPLUG_INT_EN | CRT_HOTPLUG_FORCE_DETECT | CRT_HOTPLUG_VOLTAGE_COMPARE_50 | 0x00000228, 0}, -{R, 1, "", PORT_HOTPLUG_EN, CRT_HOTPLUG_INT_EN | CRT_HOTPLUG_FORCE_DETECT | CRT_HOTPLUG_VOLTAGE_COMPARE_50 | 0x00000228, 0}, -{R, 1, "", PORT_HOTPLUG_EN, CRT_HOTPLUG_INT_EN | CRT_HOTPLUG_VOLTAGE_COMPARE_50 | 0x00000220, 0}, -{R, 1, "", PORT_HOTPLUG_STAT, 0x00000000, 0}, -{W, 1, "", PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS | 0x00000800, 0}, -{W, 1, "", PORT_HOTPLUG_EN, CRT_HOTPLUG_INT_EN | CRT_HOTPLUG_VOLTAGE_COMPARE_50 | 0x00000220, 0}, -{W, 1, "", 0x5100, 0x00000002, 0}, -{W, 1, "", 0x5104, 0x460100a1, 0}, -{R, 2, "", 0x5108, 0x00009c00, 0}, -{W, 1, "", 0x5104, 0x80000000, 0}, -{W, 1, "", 0x5104, 0x00000000, 0}, -{W, 2, "", 0x5100, 0x00000000, 0}, -{R, 1, "", _PIPEACONF, 0x00000000, 0}, -{W, 1, "", _FPA0, 0x00020e08, 0}, -{W, 1, "", _FPA1, 0x00020e08, 0}, -{W, 1, "", _DPLL_A, 0x14020003, 0}, -{W, 2, "", _DPLL_A, 0x94020003, 0}, -{R, 1, "", _PIPEACONF, 0x00000000, 0}, -{W, 1, "", _HTOTAL_A, 0x06af04ff, 0}, -{W, 1, "", _HBLANK_A, 0x06af04ff, 0}, -{W, 1, "", _HSYNC_A, 0x05d70557, 0}, -{W, 1, "", _VTOTAL_A, 0x044f03ff, 0}, -{W, 1, "", _VBLANK_A, 0x044f03ff, 0}, -{W, 1, "", _VSYNC_A, 0x04090402, 0}, -{W, 1, "", _PIPEASRC, 0x04ff03ff, 0}, -{W, 1, "", _DSPBSIZE, 0x03ff04ff, 0}, -{W, 1, "", _DSPBPOS, 0x00000000, 0}, -{W, 1, "", _PIPEACONF, 0x00000000, 0}, -{R, 1, "", _DPLL_A, 0x94020003, 0}, -{R, 1, "", _PIPEACONF, 0x00000000, 0}, -{W, 1, "", _PIPEACONF, PIPECONF_ENABLE | 0x80000000, 0}, -{R, 1, "", _PIPEASTAT, PIPE_GMBUS_INTERRUPT_STATUS | PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000a03, 0}, -{W, 1, "", _PIPEASTAT, PIPE_GMBUS_INTERRUPT_STATUS | PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000a03, 0}, -{R, 2, "", _PIPEASTAT, 0x00000000, 0}, -{R, 2, "", _PIPEASTAT, PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000203, 0}, -{W, 1, "", _PIPEASTAT, PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000203, 0}, -{R, 1, "", _PIPEASTAT, 0x00000000, 0}, -{R, 1, "", _PIPEASTAT, PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000203, 0}, -{W, 1, "", _DSPBCNTR, 0x40000000, 0}, -{R, 1, "", _DSPBCNTR, 0x40000000, 0}, -{W, 1, "", _DSPBCNTR, 0x58000000, 0}, -{W, 1, "", _DSPBSTRIDE, 0x00001400, 0}, -{W, 1, "", _DSPBADDR, 0x00020000, 0}, -{R, 2, "", DSPARB, (DSPARB_CSTART_SHIFT & 0x4) | 0x00001d9c, 0}, -{W, 1, "", INSTPM+0x20, FW_BLC_SELF_EN_MASK | 0x80000000, 0}, -{W, 1, "", FW_BLC, 0x011d011a, 0}, -{W, 1, "", FW_BLC2, 0x00000102, 0}, -{R, 1, "", TV_CTL, 0x00000000, 0}, -{W, 1, "", TV_H_CTL_1, 0x00400359, 0}, -{W, 1, "", TV_H_CTL_2, 0x80480022, 0}, -{W, 1, "", TV_H_CTL_3, 0x007c0344, 0}, -{W, 1, "", TV_V_CTL_1, 0x00f01415, 0}, -{W, 1, "", TV_V_CTL_2, 0x00060607, 0}, -{W, 1, "", TV_V_CTL_3, 0x80120001, 0}, -{W, 1, "", TV_V_CTL_4, 0x000900f0, 0}, -{W, 1, "", TV_V_CTL_5, 0x000a00f0, 0}, -{W, 1, "", TV_V_CTL_6, 0x000900f0, 0}, -{W, 1, "", TV_V_CTL_7, 0x000a00f0, 0}, -{W, 1, "", TV_SC_CTL_1, 0xc1710087, 0}, -{W, 1, "", TV_SC_CTL_2, 0x6b405140, 0}, -{W, 1, "", TV_SC_CTL_3, 0x00000000, 0}, -{W, 1, "", TV_CSC_Y, 0x0332012d, 0}, -{W, 1, "", TV_CSC_Y2, 0x07d30104, 0}, -{W, 1, "", TV_CSC_U, 0x0733052d, 0}, -{W, 1, "", TV_CSC_U2, 0x05c70200, 0}, -{W, 1, "", TV_CSC_V, 0x0340030c, 0}, -{W, 1, "", TV_CSC_V2, 0x06d00200, 0}, -{W, 1, "", TV_CLR_KNOBS, 0x00606000, 0}, -{W, 1, "", TV_CLR_LEVEL, 0x010b00e1, 0}, -{R, 1, "", _PIPEACONF, PIPECONF_ENABLE | 0x80000000, 0}, -{R, 1, "", _DSPBCNTR, 0x58000000, 0}, -{W, 1, "", _DSPBCNTR, 0x58000000, 0}, -{R, 1, "", _DSPBADDR, 0x00020000, 0}, -{W, 1, "", _DSPBADDR, 0x00020000, 0}, -{W, 1, "", _PIPEACONF, 0x00000000, 0}, -{R, 1, "", _PIPEADSL, 0x0000029e, 0}, -{R, 3, "", _PIPEADSL, 0x000003ff, 0}, -{W, 1, "", _PFA_CTL_1, 0x80000000, 0}, -{W, 1, "", _PFA_WIN_POS, 0x00360024, 0}, -{W, 1, "", _PFA_WIN_SZ, 0x02640198, 0}, -{W, 1, "", _PIPEACONF, PIPECONF_ENABLE | 0x80000000, 0}, -{W, 1, "", _DSPBCNTR, 0x58000000, 0}, -{R, 1, "", _DSPBADDR, 0x00020000, 0}, -{W, 1, "", _DSPBADDR, 0x00020000, 0}, -{W, 1, "", TV_H_LUMA_0, 0xb1403000, 0}, -{W, 1, "", TV_H_LUMA_0+0x4, 0x2e203500, 0}, -{W, 1, "", TV_H_LUMA_0+0x8, 0x35002e20, 0}, -{W, 1, "", TV_H_LUMA_0+0xc, 0x3000b140, 0}, -{W, 1, "", TV_H_LUMA_0+0x10, 0x35a0b160, 0}, -{W, 1, "", TV_H_LUMA_0+0x14, 0x2dc02e80, 0}, -{W, 1, "", TV_H_LUMA_0+0x18, 0xb1403480, 0}, -{W, 1, "", TV_H_LUMA_0+0x1c, 0xb1603000, 0}, -{W, 1, "", TV_H_LUMA_0+0x20, 0x2ea03640, 0}, -{W, 1, "", TV_H_LUMA_0+0x24, 0x34002d80, 0}, -{W, 1, "", TV_H_LUMA_0+0x28, 0x3000b120, 0}, -{W, 1, "", TV_H_LUMA_0+0x2c, 0x36e0b160, 0}, -{W, 1, "", TV_H_LUMA_0+0x30, 0x2d202ef0, 0}, -{W, 1, "", TV_H_LUMA_0+0x34, 0xb1203380, 0}, -{W, 1, "", TV_H_LUMA_0+0x38, 0xb1603000, 0}, -{W, 1, "", TV_H_LUMA_0+0x3c, 0x2f303780, 0}, -{W, 1, "", TV_H_LUMA_0+0x40, 0x33002cc0, 0}, -{W, 1, "", TV_H_LUMA_0+0x44, 0x3000b100, 0}, -{W, 1, "", TV_H_LUMA_0+0x48, 0x3820b160, 0}, -{W, 1, "", TV_H_LUMA_0+0x4c, 0x2c802f50, 0}, -{W, 1, "", TV_H_LUMA_0+0x50, 0xb10032a0, 0}, -{W, 1, "", TV_H_LUMA_0+0x54, 0xb1603000, 0}, -{W, 1, "", TV_H_LUMA_0+0x58, 0x2f9038c0, 0}, -{W, 1, "", TV_H_LUMA_0+0x5c, 0x32202c20, 0}, -{W, 1, "", TV_H_LUMA_0+0x60, 0x3000b0e0, 0}, -{W, 1, "", TV_H_LUMA_0+0x64, 0x3980b160, 0}, -{W, 1, "", TV_H_LUMA_0+0x68, 0x2bc02fc0, 0}, -{W, 1, "", TV_H_LUMA_0+0x6c, 0xb0e031c0, 0}, -{W, 1, "", TV_H_LUMA_0+0x70, 0xb1603000, 0}, -{W, 1, "", TV_H_LUMA_0+0x74, 0x2ff03a20, 0}, -{W, 1, "", TV_H_LUMA_0+0x78, 0x31602b60, 0}, -{W, 1, "", TV_H_LUMA_0+0x7c, 0xb020b0c0, 0}, -{W, 1, "", 0x68180, 0x3ae0b160, 0}, -{W, 1, "", 0x68184, 0x2b001810, 0}, -{W, 1, "", 0x68188, 0xb0c03120, 0}, -{W, 1, "", 0x6818c, 0xb140b020, 0}, -{W, 1, "", 0x68190, 0x18283ba0, 0}, -{W, 1, "", 0x68194, 0x30c02a80, 0}, -{W, 1, "", 0x68198, 0xb020b0a0, 0}, -{W, 1, "", 0x6819c, 0x3c60b140, 0}, -{W, 1, "", 0x681a0, 0x2a201838, 0}, -{W, 1, "", 0x681a4, 0xb0a03080, 0}, -{W, 1, "", 0x681a8, 0xb120b020, 0}, -{W, 1, "", 0x681ac, 0x18383d20, 0}, -{W, 1, "", 0x681b0, 0x304029c0, 0}, -{W, 1, "", 0x681b4, 0xb040b080, 0}, -{W, 1, "", 0x681b8, 0x3de0b100, 0}, -{W, 1, "", 0x681bc, 0x29601848, 0}, -{W, 1, "", 0x681c0, 0xb0803000, 0}, -{W, 1, "", 0x681c4, 0xb100b040, 0}, -{W, 1, "", 0x681c8, 0x18483ec0, 0}, -{W, 1, "", 0x681cc, 0xb0402900, 0}, -{W, 1, "", 0x681d0, 0xb040b060, 0}, -{W, 1, "", 0x681d4, 0x3f80b0c0, 0}, -{W, 1, "", 0x681d8, 0x28801858, 0}, -{W, 1, "", 0x681dc, 0xb060b080, 0}, -{W, 1, "", 0x681e0, 0xb0a0b060, 0}, -{W, 1, "", 0x681e4, 0x18602820, 0}, -{W, 1, "", 0x681e8, 0xb0a02820, 0}, -{W, 1, "", TV_H_LUMA_59, 0x0000b060, 0}, -{W, 1, "", TV_H_CHROMA_0, 0xb1403000, 0}, -{W, 1, "", TV_H_CHROMA_0+0x4, 0x2e203500, 0}, -{W, 1, "", TV_H_CHROMA_0+0x8, 0x35002e20, 0}, -{W, 1, "", TV_H_CHROMA_0+0xc, 0x3000b140, 0}, -{W, 1, "", TV_H_CHROMA_0+0x10, 0x35a0b160, 0}, -{W, 1, "", TV_H_CHROMA_0+0x14, 0x2dc02e80, 0}, -{W, 1, "", TV_H_CHROMA_0+0x18, 0xb1403480, 0}, -{W, 1, "", TV_H_CHROMA_0+0x1c, 0xb1603000, 0}, -{W, 1, "", TV_H_CHROMA_0+0x20, 0x2ea03640, 0}, -{W, 1, "", TV_H_CHROMA_0+0x24, 0x34002d80, 0}, -{W, 1, "", TV_H_CHROMA_0+0x28, 0x3000b120, 0}, -{W, 1, "", TV_H_CHROMA_0+0x2c, 0x36e0b160, 0}, -{W, 1, "", TV_H_CHROMA_0+0x30, 0x2d202ef0, 0}, -{W, 1, "", TV_H_CHROMA_0+0x34, 0xb1203380, 0}, -{W, 1, "", TV_H_CHROMA_0+0x38, 0xb1603000, 0}, -{W, 1, "", TV_H_CHROMA_0+0x3c, 0x2f303780, 0}, -{W, 1, "", TV_H_CHROMA_0+0x40, 0x33002cc0, 0}, -{W, 1, "", TV_H_CHROMA_0+0x44, 0x3000b100, 0}, -{W, 1, "", TV_H_CHROMA_0+0x48, 0x3820b160, 0}, -{W, 1, "", TV_H_CHROMA_0+0x4c, 0x2c802f50, 0}, -{W, 1, "", TV_H_CHROMA_0+0x50, 0xb10032a0, 0}, -{W, 1, "", TV_H_CHROMA_0+0x54, 0xb1603000, 0}, -{W, 1, "", TV_H_CHROMA_0+0x58, 0x2f9038c0, 0}, -{W, 1, "", TV_H_CHROMA_0+0x5c, 0x32202c20, 0}, -{W, 1, "", TV_H_CHROMA_0+0x60, 0x3000b0e0, 0}, -{W, 1, "", TV_H_CHROMA_0+0x64, 0x3980b160, 0}, -{W, 1, "", TV_H_CHROMA_0+0x68, 0x2bc02fc0, 0}, -{W, 1, "", TV_H_CHROMA_0+0x6c, 0xb0e031c0, 0}, -{W, 1, "", TV_H_CHROMA_0+0x70, 0xb1603000, 0}, -{W, 1, "", TV_H_CHROMA_0+0x74, 0x2ff03a20, 0}, -{W, 1, "", TV_H_CHROMA_0+0x78, 0x31602b60, 0}, -{W, 1, "", TV_H_CHROMA_0+0x7c, 0xb020b0c0, 0}, -{W, 1, "", 0x68280, 0x3ae0b160, 0}, -{W, 1, "", 0x68284, 0x2b001810, 0}, -{W, 1, "", 0x68288, 0xb0c03120, 0}, -{W, 1, "", 0x6828c, 0xb140b020, 0}, -{W, 1, "", 0x68290, 0x18283ba0, 0}, -{W, 1, "", 0x68294, 0x30c02a80, 0}, -{W, 1, "", 0x68298, 0xb020b0a0, 0}, -{W, 1, "", 0x6829c, 0x3c60b140, 0}, -{W, 1, "", 0x682a0, 0x2a201838, 0}, -{W, 1, "", 0x682a4, 0xb0a03080, 0}, -{W, 1, "", 0x682a8, 0xb120b020, 0}, -{W, 1, "", 0x682ac, 0x18383d20, 0}, -{W, 1, "", 0x682b0, 0x304029c0, 0}, -{W, 1, "", 0x682b4, 0xb040b080, 0}, -{W, 1, "", 0x682b8, 0x3de0b100, 0}, -{W, 1, "", 0x682bc, 0x29601848, 0}, -{W, 1, "", 0x682c0, 0xb0803000, 0}, -{W, 1, "", 0x682c4, 0xb100b040, 0}, -{W, 1, "", 0x682c8, 0x18483ec0, 0}, -{W, 1, "", 0x682cc, 0xb0402900, 0}, -{W, 1, "", 0x682d0, 0xb040b060, 0}, -{W, 1, "", 0x682d4, 0x3f80b0c0, 0}, -{W, 1, "", 0x682d8, 0x28801858, 0}, -{W, 1, "", 0x682dc, 0xb060b080, 0}, -{W, 1, "", 0x682e0, 0xb0a0b060, 0}, -{W, 1, "", 0x682e4, 0x18602820, 0}, -{W, 1, "", 0x682e8, 0xb0a02820, 0}, -{W, 1, "", TV_H_CHROMA_59, 0x0000b060, 0}, -{W, 1, "", TV_V_LUMA_0, 0x36403000, 0}, -{W, 1, "", TV_V_LUMA_0+0x4, 0x2d002cc0, 0}, -{W, 1, "", TV_V_LUMA_0+0x8, 0x30003640, 0}, -{W, 1, "", TV_V_LUMA_0+0xc, 0x2d0036c0, 0}, -{W, 1, "", TV_V_LUMA_0+0x10, 0x35c02cc0, 0}, -{W, 1, "", TV_V_LUMA_0+0x14, 0x37403000, 0}, -{W, 1, "", TV_V_LUMA_0+0x18, 0x2c802d40, 0}, -{W, 1, "", TV_V_LUMA_0+0x1c, 0x30003540, 0}, -{W, 1, "", TV_V_LUMA_0+0x20, 0x2d8037c0, 0}, -{W, 1, "", TV_V_LUMA_0+0x24, 0x34c02c40, 0}, -{W, 1, "", TV_V_LUMA_0+0x28, 0x38403000, 0}, -{W, 1, "", TV_V_LUMA_0+0x2c, 0x2bc02e00, 0}, -{W, 1, "", TV_V_LUMA_0+0x30, 0x30003440, 0}, -{W, 1, "", TV_V_LUMA_0+0x34, 0x2e2038c0, 0}, -{W, 1, "", TV_V_LUMA_0+0x38, 0x34002b80, 0}, -{W, 1, "", TV_V_LUMA_0+0x3c, 0x39803000, 0}, -{W, 1, "", TV_V_LUMA_0+0x40, 0x2b402e40, 0}, -{W, 1, "", TV_V_LUMA_0+0x44, 0x30003380, 0}, -{W, 1, "", TV_V_LUMA_0+0x48, 0x2e603a00, 0}, -{W, 1, "", TV_V_LUMA_0+0x4c, 0x33402b00, 0}, -{W, 1, "", TV_V_LUMA_0+0x50, 0x3a803040, 0}, -{W, 1, "", TV_V_LUMA_0+0x54, 0x2a802ea0, 0}, -{W, 1, "", TV_V_LUMA_0+0x58, 0x30403300, 0}, -{W, 1, "", TV_V_LUMA_0+0x5c, 0x2ec03b40, 0}, -{W, 1, "", TV_V_LUMA_0+0x60, 0x32802a40, 0}, -{W, 1, "", TV_V_LUMA_0+0x64, 0x3c003040, 0}, -{W, 1, "", TV_V_LUMA_0+0x68, 0x2a002ec0, 0}, -{W, 1, "", TV_V_LUMA_0+0x6c, 0x30803240, 0}, -{W, 1, "", TV_V_LUMA_0+0x70, 0x2ec03c80, 0}, -{W, 1, "", TV_V_LUMA_0+0x74, 0x320029c0, 0}, -{W, 1, "", TV_V_LUMA_0+0x78, 0x3d403080, 0}, -{W, 1, "", TV_V_LUMA_0+0x7c, 0x29402f00, 0}, -{W, 1, "", 0x68380, 0x308031c0, 0}, -{W, 1, "", 0x68384, 0x2f203dc0, 0}, -{W, 1, "", 0x68388, 0x31802900, 0}, -{W, 1, "", 0x6838c, 0x3e8030c0, 0}, -{W, 1, "", 0x68390, 0x28802f40, 0}, -{W, 1, "", 0x68394, 0x30c03140, 0}, -{W, 1, "", 0x68398, 0x2f203f40, 0}, -{W, 1, "", 0x6839c, 0x31402840, 0}, -{W, 1, "", 0x683a0, 0x28003100, 0}, -{W, 1, "", 0x683a4, 0x28002f00, 0}, -{W, 1, "", TV_V_LUMA_42, 0x00003100, 0}, -{W, 1, "", TV_V_CHROMA_0, 0x36403000, 0}, -{W, 1, "", TV_V_CHROMA_0+0x4, 0x2d002cc0, 0}, -{W, 1, "", TV_V_CHROMA_0+0x8, 0x30003640, 0}, -{W, 1, "", TV_V_CHROMA_0+0xc, 0x2d0036c0, 0}, -{W, 1, "", TV_V_CHROMA_0+0x10, 0x35c02cc0, 0}, -{W, 1, "", TV_V_CHROMA_0+0x14, 0x37403000, 0}, -{W, 1, "", TV_V_CHROMA_0+0x18, 0x2c802d40, 0}, -{W, 1, "", TV_V_CHROMA_0+0x1c, 0x30003540, 0}, -{W, 1, "", TV_V_CHROMA_0+0x20, 0x2d8037c0, 0}, -{W, 1, "", TV_V_CHROMA_0+0x24, 0x34c02c40, 0}, -{W, 1, "", TV_V_CHROMA_0+0x28, 0x38403000, 0}, -{W, 1, "", TV_V_CHROMA_0+0x2c, 0x2bc02e00, 0}, -{W, 1, "", TV_V_CHROMA_0+0x30, 0x30003440, 0}, -{W, 1, "", TV_V_CHROMA_0+0x34, 0x2e2038c0, 0}, -{W, 1, "", TV_V_CHROMA_0+0x38, 0x34002b80, 0}, -{W, 1, "", TV_V_CHROMA_0+0x3c, 0x39803000, 0}, -{W, 1, "", TV_V_CHROMA_0+0x40, 0x2b402e40, 0}, -{W, 1, "", TV_V_CHROMA_0+0x44, 0x30003380, 0}, -{W, 1, "", TV_V_CHROMA_0+0x48, 0x2e603a00, 0}, -{W, 1, "", TV_V_CHROMA_0+0x4c, 0x33402b00, 0}, -{W, 1, "", TV_V_CHROMA_0+0x50, 0x3a803040, 0}, -{W, 1, "", TV_V_CHROMA_0+0x54, 0x2a802ea0, 0}, -{W, 1, "", TV_V_CHROMA_0+0x58, 0x30403300, 0}, -{W, 1, "", TV_V_CHROMA_0+0x5c, 0x2ec03b40, 0}, -{W, 1, "", TV_V_CHROMA_0+0x60, 0x32802a40, 0}, -{W, 1, "", TV_V_CHROMA_0+0x64, 0x3c003040, 0}, -{W, 1, "", TV_V_CHROMA_0+0x68, 0x2a002ec0, 0}, -{W, 1, "", TV_V_CHROMA_0+0x6c, 0x30803240, 0}, -{W, 1, "", TV_V_CHROMA_0+0x70, 0x2ec03c80, 0}, -{W, 1, "", TV_V_CHROMA_0+0x74, 0x320029c0, 0}, -{W, 1, "", TV_V_CHROMA_0+0x78, 0x3d403080, 0}, -{W, 1, "", TV_V_CHROMA_0+0x7c, 0x29402f00, 0}, -{W, 1, "", 0x68480, 0x308031c0, 0}, -{W, 1, "", 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0000:00:02.0 on minor 0", 0x0, 0x0, 0}, -{0,}, -}; - -int niodefs = sizeof(iodefs) / sizeof(iodefs[0]); diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 433152c..903294d 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -40,8 +40,8 @@ static void gma_func0_init(struct device *dev)
/* IGD needs to be Bus Master */ reg32 = pci_read_config32(dev, PCI_COMMAND); - pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER); - + pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER + | PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
#if !CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT /* PCI Init, will run VBIOS */ @@ -63,7 +63,8 @@ static void gma_func0_init(struct device *dev) );
int i915lightup(u32 physbase, u32 iobase, u32 mmiobase, u32 gfx); - i915lightup(uma_memory_base, iobase, mmiobase, graphics_base); + i915lightup(pci_read_config32(dev, 0x5c) & ~0xf, + iobase, mmiobase, graphics_base); #endif
} @@ -92,7 +93,7 @@ static void gma_func1_init(struct device *dev) /* IGD needs to be Bus Master, also enable IO accesss */ reg32 = pci_read_config32(dev, PCI_COMMAND); pci_write_config32(dev, PCI_COMMAND, reg32 | - PCI_COMMAND_MASTER | PCI_COMMAND_IO); + PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
if (get_option(&val, "tft_brightness") == CB_SUCCESS) pci_write_config8(dev, 0xf4, val);
-
Vladimir Serbinenko