Change in coreboot[master]: soc/intel/(fsp_)baytrail: Initialize SPI before console init

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36407 )


Change subject: soc/intel/(fsp_)baytrail: Initialize SPI before console init
......................................................................

soc/intel/(fsp_)baytrail: Initialize SPI before console init

This makes the spi flash console function during romstage. It was
tested with the FSP baytrail codepath but it's a safe assumption that
the same fix also applies for the google mrc.bin codepath.

Tested on Intel Minnowboard Turbot.

Change-Id: If6ef0eeea902ab76d398d0218ee943e482f69b43
Signed-off-by: Arthur Heymans <[e-mail]>
---
M src/soc/intel/baytrail/romstage/romstage.c
M src/soc/intel/fsp_baytrail/romstage/romstage.c
2 files changed, 5 insertions(+), 3 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/36407/1

diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c
index 7c129e2..e06c39e 100644
--- a/src/soc/intel/baytrail/romstage/romstage.c
+++ b/src/soc/intel/baytrail/romstage/romstage.c
@@ -165,10 +165,10 @@
 	if (CONFIG(ENABLE_BUILTIN_COM1))
 		byt_config_com1_and_enable();
 
-	console_init();
-
 	spi_init();
 
+	console_init();
+
 	set_max_freq();
 
 	punit_init();
diff --git a/src/soc/intel/fsp_baytrail/romstage/romstage.c b/src/soc/intel/fsp_baytrail/romstage/romstage.c
index f347591..78aa9fc 100644
--- a/src/soc/intel/fsp_baytrail/romstage/romstage.c
+++ b/src/soc/intel/fsp_baytrail/romstage/romstage.c
@@ -171,9 +171,11 @@
 		byt_config_com1_and_enable();
 
 	post_code(0x43);
-	console_init();
 
 	spi_init();
+
+	console_init();
+
 	baytrail_rtc_init();
 
 	/* Call into mainboard. */

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: If6ef0eeea902ab76d398d0218ee943e482f69b43
Gerrit-Change-Number: 36407
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <[e-mail]>
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[Patrick Georgi (Code Review)]

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36407 )

Change subject: soc/intel/(fsp_)baytrail: Initialize SPI before console init
......................................................................


Patch Set 1: Code-Review+2


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Gerrit-Change-Number: 36407
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <[e-mail]>
Gerrit-Reviewer: Arthur Heymans <[e-mail]>
Gerrit-Reviewer: Huang Jin <[e-mail]>
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[Paul Menzel (Code Review)]

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36407 )

Change subject: soc/intel/(fsp_)baytrail: Initialize SPI before console init
......................................................................


Patch Set 1: Code-Review+1


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Gerrit-Reviewer: Arthur Heymans <[e-mail]>
Gerrit-Reviewer: Huang Jin <[e-mail]>
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[XS] Change in coreboot[master]: soc/intel/(fsp_)baytrail: Initialize SPI before console init

[Martin L Roth (Code Review)]

Martin L Roth has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/36407?usp=email )

Change subject: soc/intel/(fsp_)baytrail: Initialize SPI before console init
......................................................................


Abandoned

This patch has not been touched in over 12 months. Anyone who wants to take over work on this patch, please feel free to restore it and do any work needed to get it merged. If you create a new patch based on this work, please credit the original author.
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