Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41923 )
Change subject: [WIP] sb/intel/i82801dx: Select COMMON_FADT ......................................................................
[WIP] sb/intel/i82801dx: Select COMMON_FADT
Change-Id: Ie2fdc715e4d1af347d25b51e83189f28cd9af014 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/southbridge/intel/i82801dx/Kconfig M src/southbridge/intel/i82801dx/Makefile.inc R src/southbridge/intel/i82801dx/fadt.c 3 files changed, 3 insertions(+), 19 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/41923/1
diff --git a/src/southbridge/intel/i82801dx/Kconfig b/src/southbridge/intel/i82801dx/Kconfig index 5bea98c..a0a2ace 100644 --- a/src/southbridge/intel/i82801dx/Kconfig +++ b/src/southbridge/intel/i82801dx/Kconfig @@ -3,6 +3,7 @@ config SOUTHBRIDGE_INTEL_I82801DX bool select ACPI_INTEL_HARDWARE_SLEEP_VALUES + select COMMON_FADT select IOAPIC select HAVE_SMI_HANDLER select SOUTHBRIDGE_INTEL_COMMON_SMBUS diff --git a/src/southbridge/intel/i82801dx/Makefile.inc b/src/southbridge/intel/i82801dx/Makefile.inc index d7b2371..030f7b4 100644 --- a/src/southbridge/intel/i82801dx/Makefile.inc +++ b/src/southbridge/intel/i82801dx/Makefile.inc @@ -4,6 +4,7 @@
ramstage-y += i82801dx.c ramstage-y += ac97.c +ramstage-y += fadt.c ramstage-y += ide.c ramstage-y += lpc.c #ramstage-y += pci.c diff --git a/src/mainboard/aopen/dxplplusu/fadt.c b/src/southbridge/intel/i82801dx/fadt.c similarity index 82% rename from src/mainboard/aopen/dxplplusu/fadt.c rename to src/southbridge/intel/i82801dx/fadt.c index ad522c4..4543e92 100644 --- a/src/mainboard/aopen/dxplplusu/fadt.c +++ b/src/southbridge/intel/i82801dx/fadt.c @@ -17,22 +17,10 @@ #define S4_BIOS 0x77 #define GNVS_UPDATE 0xea
-void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) +void acpi_fill_fadt(acpi_fadt_t *fadt) { - acpi_header_t *header = &(fadt->header); u16 pmbase = pci_read_config16(pcidev_on_root(0x1f, 0), 0x40) & 0xfffe;
- memset((void *) fadt, 0, sizeof(acpi_fadt_t)); - memcpy(header->signature, "FACP", 4); - header->length = sizeof(acpi_fadt_t); - header->revision = get_acpi_table_revision(FADT); - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy(header->asl_compiler_id, ASLC, 4); - header->asl_compiler_revision = asl_revision; - - fadt->firmware_ctrl = (unsigned long) facs; - fadt->dsdt = (unsigned long) dsdt; fadt->reserved = 0; fadt->preferred_pm_profile = 0; /* PM_MOBILE; */
@@ -85,10 +73,6 @@ fadt->reset_reg.addrh = 0x0;
fadt->reset_value = 0; - fadt->x_firmware_ctl_l = (unsigned long)facs; - fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = (unsigned long)dsdt; - fadt->x_dsdt_h = 0;
fadt->x_pm1a_evt_blk.space_id = 1; fadt->x_pm1a_evt_blk.bit_width = 32; @@ -145,6 +129,4 @@ fadt->x_gpe1_blk.access_size = 0; fadt->x_gpe1_blk.addrl = 0x0; fadt->x_gpe1_blk.addrh = 0x0; - - header->checksum = acpi_checksum((void *) fadt, header->length); }
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41923
to look at the new patch set (#3).
Change subject: aopen/dxplplusu,intel/i82801dx: Select COMMON_FADT ......................................................................
aopen/dxplplusu,intel/i82801dx: Select COMMON_FADT
Move existing fadt.c file under southbridge.
Change-Id: Ie2fdc715e4d1af347d25b51e83189f28cd9af014 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/southbridge/intel/i82801dx/Kconfig M src/southbridge/intel/i82801dx/Makefile.inc R src/southbridge/intel/i82801dx/fadt.c 3 files changed, 4 insertions(+), 21 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/41923/3
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41923 )
Change subject: aopen/dxplplusu,intel/i82801dx: Select COMMON_FADT ......................................................................
Patch Set 4: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/41923/4/src/southbridge/intel/i8280... File src/southbridge/intel/i82801dx/fadt.c:
https://review.coreboot.org/c/coreboot/+/41923/4/src/southbridge/intel/i8280... PS4, Line 24: PM_UNSPECIFIED Please why don't we add 'PM_UNSPECIFIED' to src/acpi/acpi.c ( line 1262) instead ?
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41923 )
Change subject: aopen/dxplplusu,intel/i82801dx: Select COMMON_FADT ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/41923/4/src/southbridge/intel/i8280... File src/southbridge/intel/i82801dx/fadt.c:
https://review.coreboot.org/c/coreboot/+/41923/4/src/southbridge/intel/i8280... PS4, Line 24: PM_UNSPECIFIED
Please why don't we add 'PM_UNSPECIFIED' to src/acpi/acpi. […]
We don't want to trigger changes to other boards with this commit.
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41923 )
Change subject: aopen/dxplplusu,intel/i82801dx: Select COMMON_FADT ......................................................................
Patch Set 4: Code-Review+2
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41923 )
Change subject: aopen/dxplplusu,intel/i82801dx: Select COMMON_FADT ......................................................................
Patch Set 4: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/41923/4/src/southbridge/intel/i8280... File src/southbridge/intel/i82801dx/fadt.c:
https://review.coreboot.org/c/coreboot/+/41923/4/src/southbridge/intel/i8280... PS4, Line 24: PM_UNSPECIFIED
We don't want to trigger changes to other boards with this commit.
Thx. Done
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/41923 )
Change subject: aopen/dxplplusu,intel/i82801dx: Select COMMON_FADT ......................................................................
aopen/dxplplusu,intel/i82801dx: Select COMMON_FADT
Move existing fadt.c file under southbridge.
Change-Id: Ie2fdc715e4d1af347d25b51e83189f28cd9af014 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/41923 Reviewed-by: Patrick Rudolph siro@das-labor.org Reviewed-by: HAOUAS Elyes ehaouas@noos.fr Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/southbridge/intel/i82801dx/Kconfig M src/southbridge/intel/i82801dx/Makefile.inc R src/southbridge/intel/i82801dx/fadt.c 3 files changed, 4 insertions(+), 21 deletions(-)
Approvals: build bot (Jenkins): Verified HAOUAS Elyes: Looks good to me, approved Patrick Rudolph: Looks good to me, approved
diff --git a/src/southbridge/intel/i82801dx/Kconfig b/src/southbridge/intel/i82801dx/Kconfig index 5bea98c..a0a2ace 100644 --- a/src/southbridge/intel/i82801dx/Kconfig +++ b/src/southbridge/intel/i82801dx/Kconfig @@ -3,6 +3,7 @@ config SOUTHBRIDGE_INTEL_I82801DX bool select ACPI_INTEL_HARDWARE_SLEEP_VALUES + select COMMON_FADT select IOAPIC select HAVE_SMI_HANDLER select SOUTHBRIDGE_INTEL_COMMON_SMBUS diff --git a/src/southbridge/intel/i82801dx/Makefile.inc b/src/southbridge/intel/i82801dx/Makefile.inc index d7b2371..030f7b4 100644 --- a/src/southbridge/intel/i82801dx/Makefile.inc +++ b/src/southbridge/intel/i82801dx/Makefile.inc @@ -4,6 +4,7 @@
ramstage-y += i82801dx.c ramstage-y += ac97.c +ramstage-y += fadt.c ramstage-y += ide.c ramstage-y += lpc.c #ramstage-y += pci.c diff --git a/src/mainboard/aopen/dxplplusu/fadt.c b/src/southbridge/intel/i82801dx/fadt.c similarity index 81% rename from src/mainboard/aopen/dxplplusu/fadt.c rename to src/southbridge/intel/i82801dx/fadt.c index ad522c4..b497419 100644 --- a/src/mainboard/aopen/dxplplusu/fadt.c +++ b/src/southbridge/intel/i82801dx/fadt.c @@ -17,24 +17,11 @@ #define S4_BIOS 0x77 #define GNVS_UPDATE 0xea
-void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) +void acpi_fill_fadt(acpi_fadt_t *fadt) { - acpi_header_t *header = &(fadt->header); u16 pmbase = pci_read_config16(pcidev_on_root(0x1f, 0), 0x40) & 0xfffe;
- memset((void *) fadt, 0, sizeof(acpi_fadt_t)); - memcpy(header->signature, "FACP", 4); - header->length = sizeof(acpi_fadt_t); - header->revision = get_acpi_table_revision(FADT); - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy(header->asl_compiler_id, ASLC, 4); - header->asl_compiler_revision = asl_revision; - - fadt->firmware_ctrl = (unsigned long) facs; - fadt->dsdt = (unsigned long) dsdt; - fadt->reserved = 0; - fadt->preferred_pm_profile = 0; /* PM_MOBILE; */ + fadt->preferred_pm_profile = PM_UNSPECIFIED;
fadt->sci_int = 0x9;
@@ -85,10 +72,6 @@ fadt->reset_reg.addrh = 0x0;
fadt->reset_value = 0; - fadt->x_firmware_ctl_l = (unsigned long)facs; - fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = (unsigned long)dsdt; - fadt->x_dsdt_h = 0;
fadt->x_pm1a_evt_blk.space_id = 1; fadt->x_pm1a_evt_blk.bit_width = 32; @@ -145,6 +128,4 @@ fadt->x_gpe1_blk.access_size = 0; fadt->x_gpe1_blk.addrl = 0x0; fadt->x_gpe1_blk.addrh = 0x0; - - header->checksum = acpi_checksum((void *) fadt, header->length); }