Change in coreboot[master]: soc/intel/alderlake: Enable Intel FIVR RFI settings

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58878 )

Change subject: soc/intel/alderlake: Enable Intel FIVR RFI settings
......................................................................

soc/intel/alderlake: Enable Intel FIVR RFI settings

Add RFI UPD settings to mitigate RFI noise issues  and exporting
these UPDs to override via board devicetree.

BUG=b:200886627
TEST=build

Change-Id: I37bfef295fcd886d4f01abd40f9467a0791e9e34
Signed-off-by: Wisley Chen 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58878
Tested-by: build bot (Jenkins) 
Reviewed-by: Tim Wawrzynczak 
---
M src/soc/intel/alderlake/chip.h
M src/soc/intel/alderlake/fsp_params.c
2 files changed, 42 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Tim Wawrzynczak: Looks good to me, approved

diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h
index 699626b..d259442 100644
--- a/src/soc/intel/alderlake/chip.h
+++ b/src/soc/intel/alderlake/chip.h
@@ -135,6 +135,22 @@
    	     | LPM_S0i3_0 | LPM_S0i3_1 | LPM_S0i3_2 | LPM_S0i3_3 | LPM_S0i3_4,
 };

+/*
+ * FivrSpreadSpectrum:
+ * Values
+ *  0 - 0.5%, 3 - 1%, 8 - 1.5%, 18 - 2%, 28 - 3%, 34 - 4%, 39 - 5%, 44 - 6%
+ */
+enum fivr_spread_spectrum_ratio {
+	FIVR_SS_0_5 = 0,
+	FIVR_SS_1 = 3,
+	FIVR_SS_1_5 = 8,
+	FIVR_SS_2 = 18,
+	FIVR_SS_3 = 28,
+	FIVR_SS_4 = 34,
+	FIVR_SS_5 = 39,
+	FIVR_SS_6 = 44,
+};
+
 struct soc_intel_alderlake_config {

/* Common struct containing soc config data required by common code */
@@ -495,6 +511,23 @@

/* Platform Power Pmax */
    uint16_t PsysPmax;
+	/*
+	 * FivrRfiFrequency
+	 * PCODE MMIO Mailbox: Set the desired RFI frequency, in increments of 100KHz.
+	 * 0: Auto
+	 * Range varies based on XTAL clock:
+	 *   0-1918*100 KHz (Up to 191.8MHz) for 24MHz clock
+	 *   0-1535*100 KHz (Up to 153.5MHz) for 19MHz clock
+	 */
+	uint32_t FivrRfiFrequency;
+	/*
+	 * FivrSpreadSpectrum
+	 * Set the Spread Spectrum Range.
+	 *   Range: 0.5%, 1%, 1.5%, 2%, 3%, 4%, 5%, 6%.
+	 *   Each Range is translated to an encoded value for FIVR register.
+	 *   0.5% = 0, 1% = 3, 1.5% = 8, 2% = 18, 3% = 28, 4% = 34, 5% = 39, 6% = 44.
+	 */
+	uint8_t FivrSpreadSpectrum;
 };

typedef struct soc_intel_alderlake_config config_t;
diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index 9ed8acd..17edada 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -731,6 +731,14 @@
    		config->ext_fivr_settings.vnn_icc_max_ma;
 }

+static void fill_fsps_fivr_rfi_params(FSP_S_CONFIG *s_cfg,
+		const struct soc_intel_alderlake_config *config)
+{
+	/* transform from Hz to 100 KHz */
+	s_cfg->FivrRfiFrequency = config->FivrRfiFrequency / (100 * KHz);
+	s_cfg->FivrSpreadSpectrum = config->FivrSpreadSpectrum;
+}
+
 static void soc_silicon_init_params(FSP_S_CONFIG *s_cfg,
    	struct soc_intel_alderlake_config *config)
 {
@@ -761,6 +769,7 @@
    	fill_fsps_misc_power_params,
    	fill_fsps_irq_params,
    	fill_fsps_fivr_params,
+		fill_fsps_fivr_rfi_params,
    };

for (size_t i = 0; i < ARRAY_SIZE(fill_fsps_params); i++)