Attention is currently required from: Bao Zheng, Martin Roth, Marshall Dawson, Richard Spiegel, Zheng Bao, Matt Papageorge. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58871 )
Change subject: amdfwtool: Call the set_efs_table for Stoneyridge ......................................................................
Patch Set 7: Code-Review+2
(1 comment)
Patchset:
PS7:
i'll re-test this one
re-teste and it gets to the payload. output from bootblock:
coreboot-4.14-2762-g11e7308c13 Tue Nov 16 17:28:33 UTC 2021 bootblock starting (log level: 7)... Family_Model: 00670f00 Set power off after power failure. PMxC0 STATUS: 0x80800 DoReset BIT11 SPI normal read speed: 16.66 MHz SPI fast read speed: 66.66 Mhz SPI alt read speed: 16.66 MHz SPI TPM read speed: 16.66 MHz SPI100: Enabled SPI Read Mode: Dual IO (1-2-2) I2C bus 1 version 0x3132312a DW I2C bus 1 at 0xfedc3000 (400 KHz) FMAP: Found "FLASH" version 1.1 at 0x10000. FMAP: base = 0xff000000 size = 0x1000000 #areas = 4 FMAP: area COREBOOT found @ 10200 (16711168 bytes) CBFS: mcache @0x00035800 built for 15 files, used 0x328 of 0x4000 bytes CBFS: Found 'fallback/romstage' @0x80 size 0xa690 in mcache @0x0003582c BS: bootblock times (exec / console): total (unknown) / 64 ms
the show_spi_speeds_and_modes call in stoneyridge runs before the mainboard's bootblock_mainboard_init function configures the SPI interface, so this is exactly what i'd expect here. This change should also speed up the boot process on the stoneyridge chromebooks a bit, since it likely increases the spi speed when the psp gets it firmware components before coreboot starts
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Felix Held (Code Review)