Duncan Laurie has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31888 )
Change subject: soc/intel/cannonlake: Ignore GBE LTR ......................................................................
soc/intel/cannonlake: Ignore GBE LTR
Ignore integrated GBE controller LTR setting to make it wake up from s0ix with 10/100M cable attached.
BUG=b:122435844 TEST= Test on sarien platorm, after the changes sytem can wake by WOL, and also checked SLP_S0 residency can increase with 10/100M cable and battery connected.
Signed-off-by: Lijian Zhao lijian.zhao@intel.com Change-Id: Iec7dd197b8a456751f8e4dcb19e3e153f5888613 Reviewed-on: https://review.coreboot.org/c/coreboot/+/31888 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Duncan Laurie dlaurie@chromium.org --- M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/cannonlake/include/soc/pmc.h 2 files changed, 15 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Duncan Laurie: Looks good to me, approved
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 6173403..25ee5e1 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -107,6 +107,17 @@ parse_devicetree_param(config, params); }
+/* Ignore LTR value for GBE devices */ +static void ignore_gbe_ltr(void) +{ + uint8_t reg8; + uint8_t *pmcbase = pmc_mmio_regs(); + + reg8 = read8(pmcbase + LTR_IGN); + reg8 |= IGN_GBE; + write8(pmcbase + LTR_IGN, reg8); +} + /* UPD parameters to be initialized before SiliconInit */ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) { @@ -168,6 +179,7 @@ params->PchPmSlpS0VmRuntimeControl = 0; params->PchPmSlpS0Vm070VSupport = 0; params->PchPmSlpS0Vm075VSupport = 0; + ignore_gbe_ltr(); } }
diff --git a/src/soc/intel/cannonlake/include/soc/pmc.h b/src/soc/intel/cannonlake/include/soc/pmc.h index 95cca65..67854d4 100644 --- a/src/soc/intel/cannonlake/include/soc/pmc.h +++ b/src/soc/intel/cannonlake/include/soc/pmc.h @@ -145,6 +145,9 @@ #define GBLRST_CAUSE0_THERMTRIP (1 << 5) #define GBLRST_CAUSE1 0x1928
+#define LTR_IGN 0x1B0C +#define IGN_GBE (1 << 3) + #define CPPMVRIC 0x1B1C #define XTALSDQDIS (1 << 22)