Patch set updated for coreboot: riscv: enable counters via m[us]counteren

[Ronald G. Minnich]

Ronald G. Minnich ([e-mail]) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17920

-gerrit

commit 83136bd64bc95df8e11e5e8e06e3224f2c42a797
Author: Ronald G. Minnich 
Date:   Mon Dec 19 09:06:00 2016 -0800

riscv: enable counters via m[us]counteren

The user and supervisor counters could not be safely enabled
    before as the register numbers were not finalized. Now that
    everyone agrees, we can enable them. Until we are sure the
    toolchains are caught up, we use the hardcode name with
    the register names in comments. As soon as toolchains
    settle down we'll do one more pass and convert to
    the symbolic names.

Tested on lowrisc bitstream and SPIKE simulator.

Change-Id: I21fe5cac44fafe4b7806e004c179aa27541be4b6
    Signed-off-by: Ronald G. Minnich 
---
 src/arch/riscv/virtual_memory.c | 17 +++++++----------
 1 file changed, 7 insertions(+), 10 deletions(-)

diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c
index aceb72e..b9801dd 100644
--- a/src/arch/riscv/virtual_memory.c
+++ b/src/arch/riscv/virtual_memory.c
@@ -310,14 +310,11 @@ void mstatus_init(void)

set_csr(medeleg, delegate);

-	/* Enable all user/supervisor-mode counters */
-	/* We'll turn these on once lowrisc gets their bitstream up to
-	 * 1.9. Right now there's no agreement on the values for these
-	 * architectural registers.
-	 */
-	// write_csr(mscounteren, 0b111);
-	// write_csr(mucounteren, 0b111);
-
-	// for SPIKE:
-	// write_csr(/*mscounteren*/0x321, 0b111);
+	// Enable all user/supervisor-mode counters.
+	// for v1.9
+	// Until we trust our toolchain use the hardcoded constants.
+	// These were in flux and people who get the older toolchain
+	// will have difficult-to-debug failures.
+	write_csr(/*mucounteren*/0x320, 7);
+	write_csr(/*mscounteren*/0x321, 7);
 }