Change in coreboot[master]: soc/amd/cezanne/romstage: Call preload_ramstage

[Raul Rangel (Code Review)]

Attention is currently required from: Jason Glenesk, Marshall Dawson, Rob Barnes, Karthik Ramasubramanian, Felix Held.
Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58983 )

Change subject: soc/amd/cezanne/romstage: Call preload_ramstage
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Patch Set 3:

(1 comment)

Patchset:

PS3:
> Question in CB:58926

Just to add to that, We pass in the DRAM MRC address on S0 boots, and use the mmap address on S3 boots:
https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/thir...

So in the S0 case there won't be any contention. For the S3 case, I'm thinking we should preload the MRC cache using the SPI DMA controller since it's faster.