Attention is currently required from: Raul Rangel, Martin L Roth, Jon Murphy, Tim Van Patten.
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74112 )
Change subject: mb/google/myst: Enable PCIe devices in devicetree ......................................................................
Patch Set 40:
(4 comments)
Patchset:
PS40: Sorry for the last minute comment.
File src/mainboard/google/myst/port_descriptors.c:
https://review.coreboot.org/c/coreboot/+/74112/comment/38416744_9d195be5 PS40, Line 10: PCIE_ENGINE Based on schematics, we dont have PCIe based WWAN at the moment. The concerned physical lane is attached to a Trace Point. I am waiting for EE team to confirm the plan.
Since it is not used, enabling it may just add to the link training time and hence boot time. Felix, can you please confirm if my understanding is correct. If so, we can mark this engine as UNUSED_ENGINE.
https://review.coreboot.org/c/coreboot/+/74112/comment/55c77640_c9ce078b PS40, Line 41: GPIO_29 Can be removed.
This GPIO is passed by coreboot to FSP to SMU so that SMU can save and restore this GPIO during S0i3. This GPIO is in S5 domain and its state does not get reset on S0i3. Hence it does not have to be saved/restored during S0i3 by SMU. Usually we do this for GPIOs in S0 domain which loses state during S0i3.
https://review.coreboot.org/c/coreboot/+/74112/comment/799ca0b8_79b48f04 PS40, Line 53: GPIO_31 Same comment as above.
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Karthik Ramasubramanian (Code Review)