Caesar Wang has posted comments on this change. ( https://review.coreboot.org/19557 )
Change subject: rockchip/rk3399: enable DPLL SSC for DDR EMI test on bob ......................................................................
Patch Set 7:
(4 comments)
https://review.coreboot.org/#/c/19557/4/src/soc/rockchip/rk3399/clock.c File src/soc/rockchip/rk3399/clock.c:
Line 349: * extern wave table).
nit: Should you maybe do this as you're writing it here? You're only settin
Done
Line 360: * TODO find the root cause why is the delay needed, Otherwise sometime
Okay. Please change the comment to reflect that you don't know why the dela
Done
Line 373: /* Use frac mode */
Sorry, I don't understand what you mean. According to the TRM (PLL initiali
Okay, you are right here. I will set 0 for DPLL_CON2. Sorry!
Line 373: /* Use frac mode */
So we're enabling fractional mode here, but where are we setting the fracti
0x31f / (2 << 24) == 0.00024% of the intended rate (i.e. 22KHz)? =====> that's offset for frequency
I just confirm with the SSC owner, the best way is we set the 0 for DPLL_CON2.