Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/25665
Change subject: soc/amd/stoneyridge/southbridge.c: Fix bit definitions ......................................................................
soc/amd/stoneyridge/southbridge.c: Fix bit definitions
The latest public BKDG releases some previously undefined (reserved) bits. Fix these definitions, including header file where they are defined.
BUG=b:77940747 TEST=Build and boot grunt.
Change-Id: Icb5334110248d7806421200a161fa3befefcea8a Signed-off-by: Richard Spiegel richard.spiegel@silverbackltd.com --- M src/soc/amd/stoneyridge/include/soc/northbridge.h M src/soc/amd/stoneyridge/northbridge.c 2 files changed, 7 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/25665/1
diff --git a/src/soc/amd/stoneyridge/include/soc/northbridge.h b/src/soc/amd/stoneyridge/include/soc/northbridge.h index 92bce98..365a9f5 100644 --- a/src/soc/amd/stoneyridge/include/soc/northbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/northbridge.h @@ -20,6 +20,10 @@ #include <arch/io.h> #include <device/device.h>
+/* D1F1 - HDA Configuration Registers */ +#define HDA_DEV_CTRL_STATUS 0x60 +#define HDA_NO_SNOOP_EN BIT(11) + /* D18F0 - HT Configuration Registers */ #define D18F0_NODE_ID 0x60 #define D18F0_CPU_CNT 0x62 /* BKDG defines as a field in DWORD 0x60 */ diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index a7c78e6..2cefb91 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -363,9 +363,9 @@
/* disable No Snoop */ dev = dev_find_slot(0, HDA0_DEVFN); - value = pci_read_config32(dev, 0x60); - value &= ~(1 << 11); - pci_write_config32(dev, 0x60, value); + value = pci_read_config32(dev, HDA_DEV_CTRL_STATUS); + value &= ~HDA_NO_SNOOP_EN; + pci_write_config32(dev, HDA_DEV_CTRL_STATUS, value); }
void domain_read_resources(device_t dev)