Attention is currently required from: Anil Kumar K, Bora Guvendik, Cliff Huang, Felix Held, Hannah Williams, Jamie Ryu.
Subrata Banik has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84104?usp=email )
Change subject: soc/intel/common/block/pmc: Add GPE1 functions ......................................................................
Patch Set 21:
(1 comment)
File src/soc/intel/common/block/include/intelblocks/pmclib.h:
https://review.coreboot.org/c/coreboot/+/84104/comment/806d5a23_678261a5?usp... : PS11, Line 241: gpe0_mask
@subratabanik@google.com I do not see use case for pmc_enable_std_gpe and pmc_disable_std_gpe. Where is this going be used? I think we just need to be able to disable all GPE0 and GPE1 bits and also clear all of them from Coreboot boot sequence. Can we just have pmc_disable_all_gpe and remove pmc_enable_std_gpe and pmc_disable_std_gpe?
isn't `pmc_enable_std_gpe` also part of the pmc_disable_all_gpe? (ideally that should be the flow). I agree with you that we are not calling pmc_enable_std_gpe/pmc_disable_std_gpe today in BIOS flow. But those are useful APIs to be used while debugging the issue. As per my suggestion above, I have extended the GPE0 PMC_B0/Hot_Plug/PCI_exp status to GPE1 events.
@cliff.huang@intel.com, can you please implement soc_pmc_enable_std_gpe1 as suggested in my snippt ? we don't need to expose any weak function IMO.
Also as discussed please move those code outside PTL initial patch train