Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59337 )
Change subject: RFC: Unify PSP section of cezanne & picasso makefiles ......................................................................
RFC: Unify PSP section of cezanne & picasso makefiles
This isn't cleaned up or tested to very that there aren't any changes yet, but I'm trying to unify the PSP portion of the Picasso and Cezanne makefiles.
Felix, Bao, please let me know if you see any big mistakes here.
Why doesn't Picasso use multilevel?
Signed-off-by: Martin Roth gaumless@gmail.com Change-Id: I00a8a3d34afeeee08fdcec52c7fa35c885ffc7a6 --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/Makefile.inc M src/soc/amd/common/block/psp/Kconfig M src/soc/amd/common/block/psp/Makefile.inc M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/Makefile.inc 6 files changed, 240 insertions(+), 431 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/59337/1
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 3fb5085..bdd8dfe 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -70,6 +70,7 @@ select SOC_AMD_COMMON_BLOCK_UCODE select SOC_AMD_COMMON_FSP_DMI_TABLES select SOC_AMD_COMMON_FSP_PCI + select SOC_AMD_PSP_MULTILEVEL select SSE2 select UDK_2017_BINDING select X86_AMD_FIXED_MTRRS @@ -85,6 +86,10 @@ string default "soc/amd/cezanne/chipset.cb"
+config SOC_NAME + string + default "Cezanne" + config EARLY_RESERVED_DRAM_BASE hex default 0x2000000 diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index 58df740..66d11b7 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -3,6 +3,7 @@ ifeq ($(CONFIG_SOC_AMD_CEZANNE),y)
subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += psp_verstage +subdirs-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP) += ../common/psp_verstage
# Beware that all-y also adds the compilation unit to verstage on PSP all-y += config.c @@ -56,38 +57,9 @@
MAINBOARD_BLOBS_DIR:=$(top)/3rdparty/blobs/mainboard/$(MAINBOARDDIR)
-# ROMSIG Normally At ROMBASE + 0x20000 -# Overridden by CONFIG_AMD_FWM_POSITION_INDEX -# +-----------+---------------+----------------+------------+ -# |0x55AA55AA | | | | -# +-----------+---------------+----------------+------------+ -# | | PSPDIR ADDR | BIOSDIR ADDR | -# +-----------+---------------+----------------+ - -$(if $(CONFIG_AMD_FWM_POSITION_INDEX), ,\ - $(error Invalid AMD firmware position index. Check if the board sets a valid ROM size)) - -CEZANNE_FWM_POSITION=$(call int-add, \ - $(call int-subtract, 0xffffffff \ - $(call int-shift-left, \ - 0x80000 $(CONFIG_AMD_FWM_POSITION_INDEX))) 0x20000 1) - -CEZANNE_FW_A_POSITION=$(call int-add, \ - $(shell awk '$$2 == "FMAP_SECTION_FW_MAIN_A_START" {print $$3}' $(obj)/fmap_config.h) \ - 0x40) - -CEZANNE_FW_B_POSITION=$(call int-add, \ - $(shell awk '$$2 == "FMAP_SECTION_FW_MAIN_B_START" {print $$3}' $(obj)/fmap_config.h) \ - 0x40) -# -# PSP Directory Table items -# -# Certain ordering requirements apply, however these are ensured by amdfwtool. -# For more information see "AMD Platform Security Processor BIOS Architecture -# Design Guide for AMD Family 17h Processors" (PID #55758, NDA only). -# - -FIRMWARE_LOCATION=$(shell grep -e FIRMWARE_LOCATION $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}') +OPT_PSP_APCB_FILES= $(if $(APCB_SOURCES), --instance 0 --apcb $(APCB_SOURCES)) \ + $(if $(APCB_SOURCES_RECOVERY), --instance 10 --apcb $(APCB_SOURCES_RECOVERY)) \ + $(if $(APCB_SOURCES_68), --instance 18 --apcb $(APCB_SOURCES_68))
ifeq ($(CONFIG_PSP_DISABLE_POSTCODES),y) PSP_SOFTFUSE_BITS += 7 @@ -97,191 +69,6 @@ PSP_SOFTFUSE_BITS += 15 endif
-ifeq ($(CONFIG_PSP_UNLOCK_SECURE_DEBUG),y) -# Enable secure debug unlock -PSP_SOFTFUSE_BITS += 0 -OPT_TOKEN_UNLOCK="--token-unlock" -endif - -ifeq ($(CONFIG_PSP_LOAD_MP2_FW),y) -OPT_PSP_LOAD_MP2_FW="--load-mp2-fw" -else -# Disable MP2 firmware loading -PSP_SOFTFUSE_BITS += 29 -endif - -# Use additional Soft Fuse bits specified in Kconfig -PSP_SOFTFUSE_BITS += $(call strip_quotes, $(CONFIG_PSP_SOFTFUSE_BITS)) - -# type = 0x3a -ifeq ($(CONFIG_HAVE_PSP_WHITELIST_FILE),y) -PSP_WHITELIST_FILE=$(CONFIG_PSP_WHITELIST_FILE) -endif - -# -# BIOS Directory Table items - proper ordering is managed by amdfwtool -# - -# type = 0x60 -PSP_APCB_FILES=$(APCB_SOURCES) $(APCB_SOURCES_RECOVERY) - -# type = 0x61 -PSP_APOB_BASE=$(CONFIG_PSP_APOB_DRAM_ADDRESS) - -# type = 0x62 -PSP_BIOSBIN_FILE=$(obj)/amd_biospsp.img -PSP_ELF_FILE=$(objcbfs)/bootblock.elf -PSP_BIOSBIN_SIZE=$(shell $(READELF_bootblock) -l $(PSP_ELF_FILE) | grep LOAD | awk '{print $$5}') -PSP_BIOSBIN_DEST=$(shell $(READELF_bootblock) -l $(PSP_ELF_FILE) | grep LOAD | awk '{print $$3}') - -# type = 0x63 - construct APOB NV base/size from flash map -# The flashmap section used for this is expected to be named RW_MRC_CACHE -APOB_NV_SIZE=$(shell awk '$$2 == "FMAP_SECTION_RW_MRC_CACHE_SIZE" {print $$3}' $(obj)/fmap_config.h) -APOB_NV_BASE=$(shell awk '$$2 == "FMAP_SECTION_RW_MRC_CACHE_START" {print $$3}' $(obj)/fmap_config.h) - -ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y) -# type = 0x6B - PSP Shared memory location -ifneq ($(CONFIG_PSP_SHAREDMEM_SIZE),0x0) -PSP_SHAREDMEM_SIZE=$(CONFIG_PSP_SHAREDMEM_SIZE) -PSP_SHAREDMEM_BASE=$(shell awk '$$3 == "_psp_sharedmem_dram" {printf "0x" $$1}' $(objcbfs)/bootblock.map) -endif - -# type = 0x52 - PSP Bootloader Userspace Application (verstage) -PSP_VERSTAGE_FILE=$(call strip_quotes,$(CONFIG_PSP_VERSTAGE_FILE)) -PSP_VERSTAGE_SIG_FILE=$(call strip_quotes,$(CONFIG_PSP_VERSTAGE_SIGNING_TOKEN)) -endif # CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK - -# Helper function to return a value with given bit set -# Soft Fuse type = 0xb - See #55758 (NDA) for bit definitions. -set-bit=$(call int-shift-left, 1 $(call _toint,$1)) -PSP_SOFTFUSE=$(shell A=$(call int-add, \ - $(foreach bit,$(PSP_SOFTFUSE_BITS),$(call set-bit,$(bit)))); printf "0x%x" $$A) - -# -# Build the arguments to amdfwtool (order is unimportant). Missing file names -# result in empty OPT_ variables, i.e. the argument is not passed to amdfwtool. -# - -add_opt_prefix=$(if $(call strip_quotes, $(1)), $(2) $(call strip_quotes, $(1)), ) - -OPT_VERSTAGE_FILE=$(call add_opt_prefix, $(PSP_VERSTAGE_FILE), --verstage) -OPT_VERSTAGE_SIG_FILE=$(call add_opt_prefix, $(PSP_VERSTAGE_SIG_FILE), --verstage_sig) - -OPT_PSP_APCB_FILES= $(if $(APCB_SOURCES), --instance 0 --apcb $(APCB_SOURCES)) \ - $(if $(APCB_SOURCES_RECOVERY), --instance 10 --apcb $(APCB_SOURCES_RECOVERY)) \ - $(if $(APCB_SOURCES_68), --instance 18 --apcb $(APCB_SOURCES_68)) - -OPT_APOB_ADDR=$(call add_opt_prefix, $(PSP_APOB_BASE), --apob-base) -OPT_PSP_BIOSBIN_FILE=$(call add_opt_prefix, $(PSP_BIOSBIN_FILE), --bios-bin) -OPT_PSP_BIOSBIN_DEST=$(call add_opt_prefix, $(PSP_BIOSBIN_DEST), --bios-bin-dest) -OPT_PSP_BIOSBIN_SIZE=$(call add_opt_prefix, $(PSP_BIOSBIN_SIZE), --bios-uncomp-size) - -OPT_PSP_SHAREDMEM_BASE=$(call add_opt_prefix, $(PSP_SHAREDMEM_BASE), --sharedmem) -OPT_PSP_SHAREDMEM_SIZE=$(call add_opt_prefix, $(PSP_SHAREDMEM_SIZE), --sharedmem-size) -OPT_APOB_NV_SIZE=$(call add_opt_prefix, $(APOB_NV_SIZE), --apob-nv-size) -OPT_APOB_NV_BASE=$(call add_opt_prefix, $(APOB_NV_BASE),--apob-nv-base) -OPT_EFS_SPI_READ_MODE=$(call add_opt_prefix, $(CONFIG_EFS_SPI_READ_MODE), --spi-read-mode) -OPT_EFS_SPI_SPEED=$(call add_opt_prefix, $(CONFIG_EFS_SPI_SPEED), --spi-speed) -OPT_EFS_SPI_MICRON_FLAG=$(call add_opt_prefix, $(CONFIG_EFS_SPI_MICRON_FLAG), --spi-micron-flag) - -OPT_PSP_SOFTFUSE=$(call add_opt_prefix, $(PSP_SOFTFUSE), --soft-fuse) - -OPT_WHITELIST_FILE=$(call add_opt_prefix, $(PSP_WHITELIST_FILE), --whitelist) - -# Add all the files listed in the config file -POUND_SIGN=$(call strip_quotes, "#") -DEP_FILES= $(patsubst %,$(FIRMWARE_LOCATION)/%, $(shell sed -e /^$(POUND_SIGN)/d -e /*/d -e /^FIRMWARE_LOCATION/d $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}' )) - -AMDFW_COMMON_ARGS=$(OPT_PSP_APCB_FILES) \ - $(OPT_APOB_ADDR) \ - $(OPT_PSP_BIOSBIN_FILE) \ - $(OPT_PSP_BIOSBIN_DEST) \ - $(OPT_PSP_BIOSBIN_SIZE) \ - $(OPT_PSP_SOFTFUSE) \ - $(OPT_PSP_LOAD_MP2_FW) \ - --use-pspsecureos \ - --load-s0i3 \ - --combo-capable \ - $(OPT_TOKEN_UNLOCK) \ - $(OPT_WHITELIST_FILE) \ - $(OPT_PSP_SHAREDMEM_BASE) \ - $(OPT_PSP_SHAREDMEM_SIZE) \ - $(OPT_EFS_SPI_READ_MODE) \ - $(OPT_EFS_SPI_SPEED) \ - $(OPT_EFS_SPI_MICRON_FLAG) \ - --config $(CONFIG_AMDFW_CONFIG_FILE) \ - --soc-name "Cezanne" \ - --flashsize $(CONFIG_ROM_SIZE) - -$(obj)/amdfw.rom: $(call strip_quotes, $(PSP_BIOSBIN_FILE)) \ - $(PSP_VERSTAGE_FILE) \ - $(PSP_VERSTAGE_SIG_FILE) \ - $$(PSP_APCB_FILES) \ - $(DEP_FILES) \ - $(AMDFWTOOL) \ - $(obj)/fmap_config.h \ - $(objcbfs)/bootblock.elf # this target also creates the .map file - $(if $(PSP_APCB_FILES), ,$(error APCB_SOURCES is not set)) - rm -f $@ - @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" - $(AMDFWTOOL) \ - $(AMDFW_COMMON_ARGS) \ - $(OPT_APOB_NV_SIZE) \ - $(OPT_APOB_NV_BASE) \ - $(OPT_VERSTAGE_FILE) \ - $(OPT_VERSTAGE_SIG_FILE) \ - --location $(shell printf "%#x" $(CEZANNE_FWM_POSITION)) \ - --multilevel \ - --output $@ - -$(PSP_BIOSBIN_FILE): $(PSP_ELF_FILE) $(AMDCOMPRESS) - rm -f $@ - @printf " AMDCOMPRS $(subst $(obj)/,,$(@))\n" - $(AMDCOMPRESS) --infile $(PSP_ELF_FILE) --outfile $@ --compress \ - --maxsize $(PSP_BIOSBIN_SIZE) - -$(obj)/amdfw_a.rom: $(obj)/amdfw.rom - rm -f $@ - @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" - $(AMDFWTOOL) \ - $(AMDFW_COMMON_ARGS) \ - $(OPT_APOB_NV_SIZE) \ - $(OPT_APOB_NV_BASE) \ - --location $(shell printf "%#x" $(CEZANNE_FW_A_POSITION)) \ - --anywhere \ - --multilevel \ - --output $@ - -$(obj)/amdfw_b.rom: $(obj)/amdfw.rom - rm -f $@ - @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" - $(AMDFWTOOL) \ - $(AMDFW_COMMON_ARGS) \ - $(OPT_APOB_NV_SIZE) \ - $(OPT_APOB_NV_BASE) \ - --location $(shell printf "%#x" $(CEZANNE_FW_B_POSITION)) \ - --anywhere \ - --multilevel \ - --output $@ - - -cbfs-files-y += apu/amdfw -apu/amdfw-file := $(obj)/amdfw.rom -apu/amdfw-position := $(CEZANNE_FWM_POSITION) -apu/amdfw-type := raw - -ifeq ($(CONFIG_VBOOT_SLOTS_RW_AB)$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),yy) -cbfs-files-y += apu/amdfw_a -apu/amdfw_a-file := $(obj)/amdfw_a.rom -apu/amdfw_a-position := $(call strip_quotes, $(CEZANNE_FW_A_POSITION)) -apu/amdfw_a-type := raw - -cbfs-files-y += apu/amdfw_b -apu/amdfw_b-file := $(obj)/amdfw_b.rom -apu/amdfw_b-position := $(call strip_quotes, $(CEZANNE_FW_B_POSITION)) -apu/amdfw_b-type := raw -endif - cpu_microcode_bins += $(wildcard ${FIRMWARE_LOCATION}/UcodePatch_*.bin)
endif # ($(CONFIG_SOC_AMD_CEZANNE),y) diff --git a/src/soc/amd/common/block/psp/Kconfig b/src/soc/amd/common/block/psp/Kconfig index c5ec560..03cbaff 100644 --- a/src/soc/amd/common/block/psp/Kconfig +++ b/src/soc/amd/common/block/psp/Kconfig @@ -27,3 +27,9 @@ and each mainboard can choose to select an appropriate fanless or fanned set of blobs. Ask your AMD representative whether your APU is considered fanless. + +config SOC_AMD_PSP_MULTILEVEL + bool + help + Select in the chip's Kconfig if the chip supports multi-level psp + tables. diff --git a/src/soc/amd/common/block/psp/Makefile.inc b/src/soc/amd/common/block/psp/Makefile.inc index 2b407a2..0f5dbb1 100644 --- a/src/soc/amd/common/block/psp/Makefile.inc +++ b/src/soc/amd/common/block/psp/Makefile.inc @@ -5,6 +5,224 @@ smm-y += psp.c smm-y += psp_smm.c
+# ROMSIG Normally At ROMBASE + 0x20000 +# Overridden by CONFIG_AMD_FWM_POSITION_INDEX +# +-----------+---------------+----------------+------------+ +# |0x55AA55AA | | | | +# +-----------+---------------+----------------+------------+ +# | | PSPDIR ADDR | BIOSDIR ADDR | +# +-----------+---------------+----------------+ + +$(if $(CONFIG_AMD_FWM_POSITION_INDEX), ,\ + $(error Invalid AMD firmware position index. Check if the board sets a valid ROM size)) + +FWM_POSITION=$(call int-add, \ + $(call int-subtract, 0xffffffff \ + $(call int-shift-left, \ + 0x80000 $(CONFIG_AMD_FWM_POSITION_INDEX))) 0x20000 1) + +FW_A_POSITION=$(call int-add, \ + $(shell awk '$$2 == "FMAP_SECTION_FW_MAIN_A_START" {print $$3}' $(obj)/fmap_config.h) \ + 0x40) + +FW_B_POSITION=$(call int-add, \ + $(shell awk '$$2 == "FMAP_SECTION_FW_MAIN_B_START" {print $$3}' $(obj)/fmap_config.h) \ + 0x40) +# +# PSP Directory Table items +# +# Certain ordering requirements apply, however these are ensured by amdfwtool. +# For more information see "AMD Platform Security Processor BIOS Architecture +# Design Guide for AMD Family 17h Processors" (PID #55758, NDA only). +# + +FIRMWARE_LOCATION=$(shell grep -e FIRMWARE_LOCATION $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}') + +ifeq ($(CONFIG_PSP_UNLOCK_SECURE_DEBUG),y) +# Enable secure debug unlock +PSP_SOFTFUSE_BITS += 0 +OPT_TOKEN_UNLOCK="--token-unlock" +endif + +ifeq ($(CONFIG_PSP_LOAD_MP2_FW),y) +OPT_PSP_LOAD_MP2_FW="--load-mp2-fw" +else +# Disable MP2 firmware loading +PSP_SOFTFUSE_BITS += 29 +endif + +# Use additional Soft Fuse bits specified in Kconfig +PSP_SOFTFUSE_BITS += $(call strip_quotes, $(CONFIG_PSP_SOFTFUSE_BITS)) + +ifeq ($(CONFIG_PSP_LOAD_S0I3_FW),y) +OPT_PSP_LOAD_S0I3_FW="--load-s0i3" +endif + +# type = 0x3a +ifeq ($(CONFIG_HAVE_PSP_WHITELIST_FILE),y) +PSP_WHITELIST_FILE=$(CONFIG_PSP_WHITELIST_FILE) +endif + +# +# BIOS Directory Table items - proper ordering is managed by amdfwtool +# + +# type = 0x60 +PSP_APCB_FILES=$(APCB_SOURCES) $(APCB_SOURCES_RECOVERY) + +# type = 0x61 +PSP_APOB_BASE=$(CONFIG_PSP_APOB_DRAM_ADDRESS) + +# type = 0x62 +PSP_BIOSBIN_FILE=$(obj)/amd_biospsp.img +PSP_ELF_FILE=$(objcbfs)/bootblock.elf +PSP_BIOSBIN_SIZE=$(shell $(READELF_bootblock) -l $(PSP_ELF_FILE) | grep LOAD | awk '{print $$5}') +PSP_BIOSBIN_DEST=$(shell $(READELF_bootblock) -l $(PSP_ELF_FILE) | grep LOAD | awk '{print $$3}') + +# type = 0x63 - construct APOB NV base/size from flash map +# The flashmap section used for this is expected to be named RW_MRC_CACHE +APOB_NV_SIZE=$(shell awk '$$2 == "FMAP_SECTION_RW_MRC_CACHE_SIZE" {print $$3}' $(obj)/fmap_config.h) +APOB_NV_BASE=$(shell awk '$$2 == "FMAP_SECTION_RW_MRC_CACHE_START" {print $$3}' $(obj)/fmap_config.h) + +ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y) +# type = 0x6B - PSP Shared memory location +ifneq ($(CONFIG_PSP_SHAREDMEM_SIZE),0x0) +PSP_SHAREDMEM_SIZE=$(CONFIG_PSP_SHAREDMEM_SIZE) +PSP_SHAREDMEM_BASE=$(shell awk '$$3 == "_psp_sharedmem_dram" {printf "0x" $$1}' $(objcbfs)/bootblock.map) +endif + +# type = 0x52 - PSP Bootloader Userspace Application (verstage) +PSP_VERSTAGE_FILE=$(call strip_quotes,$(CONFIG_PSP_VERSTAGE_FILE)) +PSP_VERSTAGE_SIG_FILE=$(call strip_quotes,$(CONFIG_PSP_VERSTAGE_SIGNING_TOKEN)) +endif # CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK + +# Helper function to return a value with given bit set +# Soft Fuse type = 0xb - See #55758 (NDA) for bit definitions. +set-bit=$(call int-shift-left, 1 $(call _toint,$1)) +PSP_SOFTFUSE=$(shell A=$(call int-add, \ + $(foreach bit,$(PSP_SOFTFUSE_BITS),$(call set-bit,$(bit)))); printf "0x%x" $$A) + +# +# Build the arguments to amdfwtool (order is unimportant). Missing file names +# result in empty OPT_ variables, i.e. the argument is not passed to amdfwtool. +# + +add_opt_prefix=$(if $(call strip_quotes, $(1)), $(2) $(call strip_quotes, $(1)), ) + +OPT_VERSTAGE_FILE=$(call add_opt_prefix, $(PSP_VERSTAGE_FILE), --verstage) +OPT_VERSTAGE_SIG_FILE=$(call add_opt_prefix, $(PSP_VERSTAGE_SIG_FILE), --verstage_sig) + +OPT_APOB_ADDR=$(call add_opt_prefix, $(PSP_APOB_BASE), --apob-base) +OPT_PSP_BIOSBIN_FILE=$(call add_opt_prefix, $(PSP_BIOSBIN_FILE), --bios-bin) +OPT_PSP_BIOSBIN_DEST=$(call add_opt_prefix, $(PSP_BIOSBIN_DEST), --bios-bin-dest) +OPT_PSP_BIOSBIN_SIZE=$(call add_opt_prefix, $(PSP_BIOSBIN_SIZE), --bios-uncomp-size) + +OPT_PSP_SHAREDMEM_BASE=$(call add_opt_prefix, $(PSP_SHAREDMEM_BASE), --sharedmem) +OPT_PSP_SHAREDMEM_SIZE=$(call add_opt_prefix, $(PSP_SHAREDMEM_SIZE), --sharedmem-size) +OPT_APOB_NV_SIZE=$(call add_opt_prefix, $(APOB_NV_SIZE), --apob-nv-size) +OPT_APOB_NV_BASE=$(call add_opt_prefix, $(APOB_NV_BASE),--apob-nv-base) +OPT_EFS_SPI_READ_MODE=$(call add_opt_prefix, $(CONFIG_EFS_SPI_READ_MODE), --spi-read-mode) +OPT_EFS_SPI_SPEED=$(call add_opt_prefix, $(CONFIG_EFS_SPI_SPEED), --spi-speed) +OPT_EFS_SPI_MICRON_FLAG=$(call add_opt_prefix, $(CONFIG_EFS_SPI_MICRON_FLAG), --spi-micron-flag) +OPT_PSP_MULTILEVEL=$(call add_opt_prefix, $(CONFIG_SOC_AMD_PSP_MULTILEVEL), --multilevel) +OPT_PSP_SOFTFUSE=$(call add_opt_prefix, $(PSP_SOFTFUSE), --soft-fuse) + +OPT_WHITELIST_FILE=$(call add_opt_prefix, $(PSP_WHITELIST_FILE), --whitelist) + +# Add all the files listed in the config file +POUND_SIGN=$(call strip_quotes, "#") +DEP_FILES= $(patsubst %,$(FIRMWARE_LOCATION)/%, $(shell sed -e /^$(POUND_SIGN)/d -e /*/d -e /^FIRMWARE_LOCATION/d $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}' )) + +AMDFW_COMMON_ARGS=$(OPT_PSP_APCB_FILES) \ + $(OPT_APOB_ADDR) \ + $(OPT_PSP_BIOSBIN_FILE) \ + $(OPT_PSP_BIOSBIN_DEST) \ + $(OPT_PSP_BIOSBIN_SIZE) \ + $(OPT_PSP_SOFTFUSE) \ + --use-pspsecureos \ + $(OPT_PSP_LOAD_MP2_FW) \ + $(OPT_PSP_LOAD_S0I3_FW) \ + $(OPT_WHITELIST_FILE) \ + $(OPT_PSP_SHAREDMEM_BASE) \ + $(OPT_PSP_SHAREDMEM_SIZE) \ + --combo-capable \ + $(OPT_TOKEN_UNLOCK) \ + $(OPT_EFS_SPI_READ_MODE) \ + $(OPT_EFS_SPI_SPEED) \ + $(OPT_EFS_SPI_MICRON_FLAG) \ + --config $(CONFIG_AMDFW_CONFIG_FILE) \ + --soc-name "$(CONFIG_SOC_NAME)" \ + --flashsize $(CONFIG_ROM_SIZE) + +$(obj)/amdfw.rom: $(call strip_quotes, $(PSP_BIOSBIN_FILE)) \ + $(PSP_VERSTAGE_FILE) \ + $(PSP_VERSTAGE_SIG_FILE) \ + $$(PSP_APCB_FILES) \ + $(DEP_FILES) \ + $(AMDFWTOOL) \ + $(obj)/fmap_config.h \ + $(objcbfs)/bootblock.elf # this target also creates the .map file + $(if $(PSP_APCB_FILES), ,$(error APCB_SOURCES is not set)) + rm -f $@ + @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" + $(AMDFWTOOL) \ + $(AMDFW_COMMON_ARGS) \ + $(OPT_APOB_NV_SIZE) \ + $(OPT_APOB_NV_BASE) \ + $(OPT_VERSTAGE_FILE) \ + $(OPT_VERSTAGE_SIG_FILE) \ + $(OPT_PSP_MULTILEVEL) \ + --location $(shell printf "%#x" $(FWM_POSITION)) \ + --output $@ + +$(PSP_BIOSBIN_FILE): $(PSP_ELF_FILE) $(AMDCOMPRESS) + rm -f $@ + @printf " AMDCOMPRS $(subst $(obj)/,,$(@))\n" + $(AMDCOMPRESS) --infile $(PSP_ELF_FILE) --outfile $@ --compress \ + --maxsize $(PSP_BIOSBIN_SIZE) + +$(obj)/amdfw_a.rom: $(obj)/amdfw.rom + rm -f $@ + @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" + $(AMDFWTOOL) \ + $(AMDFW_COMMON_ARGS) \ + $(OPT_APOB_NV_SIZE) \ + $(OPT_APOB_NV_BASE) \ + $(OPT_PSP_MULTILEVEL) \ + --location $(shell printf "%#x" $(FW_A_POSITION)) \ + --anywhere \ + --output $@ + +$(obj)/amdfw_b.rom: $(obj)/amdfw.rom + rm -f $@ + @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" + $(AMDFWTOOL) \ + $(AMDFW_COMMON_ARGS) \ + $(OPT_APOB_NV_SIZE) \ + $(OPT_APOB_NV_BASE) \ + $(OPT_PSP_MULTILEVEL) \ + --location $(shell printf "%#x" $(FW_B_POSITION)) \ + --anywhere \ + --output $@ + + +cbfs-files-y += apu/amdfw +apu/amdfw-file := $(obj)/amdfw.rom +apu/amdfw-position := $(FWM_POSITION) +apu/amdfw-type := raw + +ifeq ($(CONFIG_VBOOT_SLOTS_RW_AB)$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),yy) +cbfs-files-y += apu/amdfw_a +apu/amdfw_a-file := $(obj)/amdfw_a.rom +apu/amdfw_a-position := $(call strip_quotes, $(FW_A_POSITION)) +apu/amdfw_a-type := raw + +cbfs-files-y += apu/amdfw_b +apu/amdfw_b-file := $(obj)/amdfw_b.rom +apu/amdfw_b-position := $(call strip_quotes, $(FW_B_POSITION)) +apu/amdfw_b-type := raw +endif + endif # CONFIG_SOC_AMD_COMMON_BLOCK_PSP
ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN1),y) diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 92607a3..af1176c 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -81,6 +81,10 @@ string default "soc/amd/picasso/chipset.cb"
+config SOC_NAME + string + default "Picasso" + config FSP_M_FILE string "FSP-M (memory init) binary path and filename" depends on ADD_FSP_BINARIES diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 7db4719..5897016 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -3,7 +3,7 @@ ifeq ($(CONFIG_SOC_AMD_PICASSO),y)
subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += psp_verstage -subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += ../common/psp_verstage +subdirs-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP) += ../common/psp_verstage
# Beware that all-y also adds the compilation unit to verstage on PSP all-y += config.c @@ -62,225 +62,14 @@
MAINBOARD_BLOBS_DIR:=$(top)/3rdparty/blobs/mainboard/$(MAINBOARDDIR)
-# ROMSIG Normally At ROMBASE + 0x20000 -# Overridden by CONFIG_AMD_FWM_POSITION_INDEX -# +-----------+---------------+----------------+------------+ -# |0x55AA55AA | | | | -# +-----------+---------------+----------------+------------+ -# | | PSPDIR ADDR | BIOSDIR ADDR | -# +-----------+---------------+----------------+ - -$(if $(CONFIG_AMD_FWM_POSITION_INDEX), ,\ - $(error Invalid AMD firmware position index. Check if the board sets a valid ROM size)) - -PICASSO_FWM_POSITION=$(call int-add, \ - $(call int-subtract, 0xffffffff \ - $(call int-shift-left, \ - 0x80000 $(CONFIG_AMD_FWM_POSITION_INDEX))) 0x20000 1) - -# -# PSP Directory Table items -# -# Certain ordering requirements apply, however these are ensured by amdfwtool. -# For more information see "AMD Platform Security Processor BIOS Architecture -# Design Guide for AMD Family 17h Processors" (PID #55758, NDA only). -# - -FIRMWARE_LOCATION=$(shell grep -e FIRMWARE_LOCATION $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}') - -ifeq ($(CONFIG_PSP_UNLOCK_SECURE_DEBUG),y) -# Enable secure debug unlock -PSP_SOFTFUSE_BITS += 0 -OPT_TOKEN_UNLOCK="--token-unlock" -endif - -ifeq ($(CONFIG_PSP_LOAD_MP2_FW),y) -OPT_PSP_LOAD_MP2_FW="--load-mp2-fw" -else -# Disable MP2 firmware loading -PSP_SOFTFUSE_BITS += 29 -endif - -# Use additional Soft Fuse bits specified in Kconfig -PSP_SOFTFUSE_BITS += $(call strip_quotes, $(CONFIG_PSP_SOFTFUSE_BITS)) - -ifeq ($(CONFIG_PSP_LOAD_S0I3_FW),y) -OPT_PSP_LOAD_S0I3_FW="--load-s0i3" -endif - -# type = 0x3a -ifeq ($(CONFIG_HAVE_PSP_WHITELIST_FILE),y) -PSP_WHITELIST_FILE=$(CONFIG_PSP_WHITELIST_FILE) -endif -# -# BIOS Directory Table items - proper ordering is managed by amdfwtool -# - -# type = 0x60 -PSP_APCB_FILES=$(APCB_SOURCES) - -# type = 0x61 -PSP_APOB_BASE=$(CONFIG_PSP_APOB_DRAM_ADDRESS) - -# type = 0x62 -PSP_BIOSBIN_FILE=$(obj)/amd_biospsp.img -PSP_ELF_FILE=$(objcbfs)/bootblock.elf -PSP_BIOSBIN_SIZE=$(shell $(READELF_bootblock) -l $(PSP_ELF_FILE) | grep LOAD | awk '{print $$5}') -PSP_BIOSBIN_DEST=$(shell $(READELF_bootblock) -l $(PSP_ELF_FILE) | grep LOAD | awk '{print $$3}') -# type = 0x63 - construct APOB NV base/size from flash map -# The flashmap section used for this is expected to be named RW_MRC_CACHE -APOB_NV_SIZE=$(shell awk '$$2 == "FMAP_SECTION_RW_MRC_CACHE_SIZE" {print $$3}' $(obj)/fmap_config.h) -APOB_NV_BASE=$(shell awk '$$2 == "FMAP_SECTION_RW_MRC_CACHE_START" {print $$3}' $(obj)/fmap_config.h) - -ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y) -# type = 0x6B - PSP Shared memory location -ifneq ($(CONFIG_PSP_SHAREDMEM_SIZE),0x0) -PSP_SHAREDMEM_SIZE=$(CONFIG_PSP_SHAREDMEM_SIZE) -PSP_SHAREDMEM_BASE=$(shell awk '$$3 == "_psp_sharedmem_dram" {printf "0x" $$1}' $(objcbfs)/bootblock.map) -endif - -# type = 0x52 - PSP Bootloader Userspace Application (verstage) -PSP_VERSTAGE_FILE=$(call strip_quotes,$(CONFIG_PSP_VERSTAGE_FILE)) -PSP_VERSTAGE_SIG_FILE=$(call strip_quotes,$(CONFIG_PSP_VERSTAGE_SIGNING_TOKEN)) -endif # CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK - - -# Helper function to return a value with given bit set -# Soft Fuse type = 0xb - See #55758 (NDA) for bit definitions. -set-bit=$(call int-shift-left, 1 $(call _toint,$1)) -PSP_SOFTFUSE=$(shell A=$(call int-add, \ - $(foreach bit,$(PSP_SOFTFUSE_BITS),$(call set-bit,$(bit)))); printf "0x%x" $$A) - -# -# Build the arguments to amdfwtool (order is unimportant). Missing file names -# result in empty OPT_ variables, i.e. the argument is not passed to amdfwtool. -# - -add_opt_prefix=$(if $(call strip_quotes, $(1)), $(2) $(call strip_quotes, $(1)), ) - -OPT_VERSTAGE_FILE=$(call add_opt_prefix, $(PSP_VERSTAGE_FILE), --verstage) -OPT_VERSTAGE_SIG_FILE=$(call add_opt_prefix, $(PSP_VERSTAGE_SIG_FILE), --verstage_sig) - OPT_PSP_APCB_FILES=$(foreach i, $(shell seq $(words $(PSP_APCB_FILES))), \ $(call add_opt_prefix, $(word $(i), $(PSP_APCB_FILES)), \ --instance $(shell printf "%x" $$(($(i)-1))) --apcb ) ) -OPT_PSP_APCB_FILES_BK=$(foreach i, $(shell seq $(words $(PSP_APCB_FILES))), \ + +OPT_PSP_APCB_FILES+=$(foreach i, $(shell seq $(words $(PSP_APCB_FILES))), \ $(call add_opt_prefix, $(word $(i), $(PSP_APCB_FILES)), \ --instance $(shell printf "1%x" $$(($(i)-1))) --apcb ) )
-OPT_APOB_ADDR=$(call add_opt_prefix, $(PSP_APOB_BASE), --apob-base) -OPT_PSP_BIOSBIN_FILE=$(call add_opt_prefix, $(PSP_BIOSBIN_FILE), --bios-bin) -OPT_PSP_BIOSBIN_DEST=$(call add_opt_prefix, $(PSP_BIOSBIN_DEST), --bios-bin-dest) -OPT_PSP_BIOSBIN_SIZE=$(call add_opt_prefix, $(PSP_BIOSBIN_SIZE), --bios-uncomp-size) - -OPT_PSP_SHAREDMEM_BASE=$(call add_opt_prefix, $(PSP_SHAREDMEM_BASE), --sharedmem) -OPT_PSP_SHAREDMEM_SIZE=$(call add_opt_prefix, $(PSP_SHAREDMEM_SIZE), --sharedmem-size) -OPT_APOB_NV_SIZE=$(call add_opt_prefix, $(APOB_NV_SIZE), --apob-nv-size) -OPT_APOB_NV_BASE=$(call add_opt_prefix, $(APOB_NV_BASE),--apob-nv-base) -OPT_EFS_SPI_READ_MODE=$(call add_opt_prefix, $(CONFIG_EFS_SPI_READ_MODE), --spi-read-mode) -OPT_EFS_SPI_SPEED=$(call add_opt_prefix, $(CONFIG_EFS_SPI_SPEED), --spi-speed) -OPT_EFS_SPI_MICRON_FLAG=$(call add_opt_prefix, $(CONFIG_EFS_SPI_MICRON_FLAG), --spi-micron-flag) - -OPT_PSP_SOFTFUSE=$(call add_opt_prefix, $(PSP_SOFTFUSE), --soft-fuse) - -ifeq ($(CONFIG_VBOOT),) -OPT_APOB0_NV_SIZE=$(OPT_APOB_NV_SIZE) -OPT_APOB0_NV_BASE=$(OPT_APOB_NV_BASE) -endif - -OPT_WHITELIST_FILE=$(call add_opt_prefix, $(PSP_WHITELIST_FILE), --whitelist) - -# Add all the files listed in the config file -POUND_SIGN=$(call strip_quotes, "#") -DEP_FILES= $(patsubst %,$(FIRMWARE_LOCATION)/%, $(shell sed -e /^$(POUND_SIGN)/d -e /^FIRMWARE_LOCATION/d $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}' )) - -AMDFW_COMMON_ARGS=$(OPT_PSP_APCB_FILES) \ - $(OPT_PSP_APCB_FILES_BK) \ - $(OPT_APOB_ADDR) \ - $(OPT_PSP_BIOSBIN_FILE) \ - $(OPT_PSP_BIOSBIN_DEST) \ - $(OPT_PSP_BIOSBIN_SIZE) \ - $(OPT_PSP_SOFTFUSE) \ - --use-pspsecureos \ - $(OPT_PSP_LOAD_MP2_FW) \ - $(OPT_PSP_LOAD_S0I3_FW) \ - $(OPT_WHITELIST_FILE) \ - $(OPT_PSP_SHAREDMEM_BASE) \ - $(OPT_PSP_SHAREDMEM_SIZE) \ - --combo-capable \ - $(OPT_TOKEN_UNLOCK) \ - $(OPT_EFS_SPI_READ_MODE) \ - $(OPT_EFS_SPI_SPEED) \ - $(OPT_EFS_SPI_MICRON_FLAG) \ - --config $(CONFIG_AMDFW_CONFIG_FILE) \ - --soc-name "Picasso" \ - --flashsize $(CONFIG_ROM_SIZE) - -$(obj)/amdfw.rom: $(call strip_quotes, $(PSP_BIOSBIN_FILE)) \ - $(PSP_VERSTAGE_FILE) \ - $(PSP_VERSTAGE_SIG_FILE) \ - $$(PSP_APCB_FILES) \ - $(DEP_FILES) \ - $(AMDFWTOOL) \ - $(obj)/fmap_config.h \ - $(objcbfs)/bootblock.elf # this target also creates the .map file - $(if $(PSP_APCB_FILES), ,$(error APCB_SOURCES is not set)) - rm -f $@ - @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" - $(AMDFWTOOL) \ - $(AMDFW_COMMON_ARGS) \ - $(OPT_APOB0_NV_SIZE) \ - $(OPT_APOB0_NV_BASE) \ - $(OPT_VERSTAGE_FILE) \ - $(OPT_VERSTAGE_SIG_FILE) \ - --location $(shell printf "%#x" $(PICASSO_FWM_POSITION)) \ - --output $@ - -$(PSP_BIOSBIN_FILE): $(PSP_ELF_FILE) $(AMDCOMPRESS) - rm -f $@ - @printf " AMDCOMPRS $(subst $(obj)/,,$(@))\n" - $(AMDCOMPRESS) --infile $(PSP_ELF_FILE) --outfile $@ --compress \ - --maxsize $(PSP_BIOSBIN_SIZE) - -$(obj)/amdfw_a.rom: $(obj)/amdfw.rom - rm -f $@ - @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" - $(AMDFWTOOL) \ - $(AMDFW_COMMON_ARGS) \ - $(OPT_APOB_NV_SIZE) \ - $(OPT_APOB_NV_BASE) \ - --location $(shell printf "%#x" $(CONFIG_PICASSO_FW_A_POSITION)) \ - --anywhere \ - --output $@ - -$(obj)/amdfw_b.rom: $(obj)/amdfw.rom - rm -f $@ - @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" - $(AMDFWTOOL) \ - $(AMDFW_COMMON_ARGS) \ - $(OPT_APOB_NV_SIZE) \ - $(OPT_APOB_NV_BASE) \ - --location $(shell printf "%#x" $(CONFIG_PICASSO_FW_B_POSITION)) \ - --anywhere \ - --output $@ - -cbfs-files-y += apu/amdfw -apu/amdfw-file := $(obj)/amdfw.rom -apu/amdfw-position := $(PICASSO_FWM_POSITION) -apu/amdfw-type := raw - -ifeq ($(CONFIG_VBOOT_SLOTS_RW_AB)$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),yy) -cbfs-files-y += apu/amdfw_a -apu/amdfw_a-file := $(obj)/amdfw_a.rom -apu/amdfw_a-position := $(call strip_quotes, $(CONFIG_PICASSO_FW_A_POSITION)) -apu/amdfw_a-type := raw - -cbfs-files-y += apu/amdfw_b -apu/amdfw_b-file := $(obj)/amdfw_b.rom -apu/amdfw_b-position := $(call strip_quotes, $(CONFIG_PICASSO_FW_B_POSITION)) -apu/amdfw_b-type := raw -endif - cpu_microcode_bins += $(wildcard ${FIRMWARE_LOCATION}/UcodePatch_*.bin)
endif # ($(CONFIG_SOC_AMD_PICASSO),y)
-
Martin Roth (Code Review)