Change in coreboot[master]: WIP libpayload: Parse DDR Information through coreboot tables WIP

[build bot (Jenkins) (Code Review)]

Attention is currently required from: Ravi kumar, Shelley Chen, mturney mturney, Julius Werner.
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59193 )

Change subject: WIP libpayload: Parse DDR Information through coreboot tables WIP
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Patch Set 3:

(4 comments)

File payloads/libpayload/libc/coreboot.c:

Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133417):
https://review.coreboot.org/c/coreboot/+/59193/comment/39866706_726ad101 
PS3, Line 357:                         cb_parse_mem_chip_info(ptr, info);
code indent should use tabs where possible

Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133417):
https://review.coreboot.org/c/coreboot/+/59193/comment/74914271_60d91340 
PS3, Line 357:                         cb_parse_mem_chip_info(ptr, info);
please, no spaces at the start of a line

Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133417):
https://review.coreboot.org/c/coreboot/+/59193/comment/4115b438_b8ae8001 
PS3, Line 358:                         break;
code indent should use tabs where possible

Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133417):
https://review.coreboot.org/c/coreboot/+/59193/comment/9b3092fd_240a72df 
PS3, Line 358:                         break;
please, no spaces at the start of a line