Change in coreboot[master]: soc/intel/alderlake: Add Alder Lake P IGD device IDs

[Subrata Banik (Code Review)]

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61441 )

Change subject: soc/intel/alderlake: Add Alder Lake P IGD device IDs
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soc/intel/alderlake: Add Alder Lake P IGD device IDs

This patch adds additional IGD device IDs as per document 638514.

BUG=b:216420554
TEST=coreboot is able to probe the IGD device during PCI enumeration.

Change-Id: I0cafe92581c454da5e4aeafd7ad52f0e65370b11
Signed-off-by: Kane Chen 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61441
Reviewed-by: Subrata Banik 
Reviewed-by: Sridhar Siricilla 
Tested-by: build bot (Jenkins) 
---
M src/include/device/pci_ids.h
M src/soc/intel/alderlake/bootblock/report_platform.c
M src/soc/intel/common/block/graphics/graphics.c
3 files changed, 9 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Sridhar Siricilla: Looks good to me, but someone else must approve
  Subrata Banik: Looks good to me, approved

diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index 22962c3..6b53bb0 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -3902,6 +3902,9 @@
 #define PCI_DEVICE_ID_INTEL_ADL_P_GT2_4			0x46a8
 #define PCI_DEVICE_ID_INTEL_ADL_P_GT2_5			0x46b3
 #define PCI_DEVICE_ID_INTEL_ADL_P_GT2_6			0x46a6
+#define PCI_DEVICE_ID_INTEL_ADL_P_GT2_7			0x4628
+#define PCI_DEVICE_ID_INTEL_ADL_P_GT2_8			0x46b1
+#define PCI_DEVICE_ID_INTEL_ADL_P_GT2_9			0x4626
 #define PCI_DEVICE_ID_INTEL_ADL_S_GT1			0x4680
 #define PCI_DEVICE_ID_INTEL_ADL_M_GT1			0x46c0
 #define PCI_DEVICE_ID_INTEL_ADL_M_GT2			0x46aa
diff --git a/src/soc/intel/alderlake/bootblock/report_platform.c b/src/soc/intel/alderlake/bootblock/report_platform.c
index 5c695f2..b419dda 100644
--- a/src/soc/intel/alderlake/bootblock/report_platform.c
+++ b/src/soc/intel/alderlake/bootblock/report_platform.c
@@ -115,6 +115,9 @@
    { PCI_DEVICE_ID_INTEL_ADL_P_GT2_4, "Alderlake P GT2" },
    { PCI_DEVICE_ID_INTEL_ADL_P_GT2_5, "Alderlake P GT2" },
    { PCI_DEVICE_ID_INTEL_ADL_P_GT2_6, "Alderlake P GT2" },
+	{ PCI_DEVICE_ID_INTEL_ADL_P_GT2_7, "Alderlake P GT2" },
+	{ PCI_DEVICE_ID_INTEL_ADL_P_GT2_8, "Alderlake P GT2" },
+	{ PCI_DEVICE_ID_INTEL_ADL_P_GT2_9, "Alderlake P GT2" },
    { PCI_DEVICE_ID_INTEL_ADL_M_GT1, "Alderlake M GT1" },
    { PCI_DEVICE_ID_INTEL_ADL_M_GT2, "Alderlake M GT2" },
    { PCI_DEVICE_ID_INTEL_ADL_M_GT3, "Alderlake M GT3" },
diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c
index 1db0e46..4b0b4c4 100644
--- a/src/soc/intel/common/block/graphics/graphics.c
+++ b/src/soc/intel/common/block/graphics/graphics.c
@@ -307,6 +307,9 @@
    PCI_DEVICE_ID_INTEL_ADL_P_GT2_4,
    PCI_DEVICE_ID_INTEL_ADL_P_GT2_5,
    PCI_DEVICE_ID_INTEL_ADL_P_GT2_6,
+	PCI_DEVICE_ID_INTEL_ADL_P_GT2_7,
+	PCI_DEVICE_ID_INTEL_ADL_P_GT2_8,
+	PCI_DEVICE_ID_INTEL_ADL_P_GT2_9,
    PCI_DEVICE_ID_INTEL_ADL_S_GT1,
    PCI_DEVICE_ID_INTEL_ADL_M_GT1,
    PCI_DEVICE_ID_INTEL_ADL_M_GT2,