[XS] Change in coreboot[main]: soc/intel/ehl/fsp_params: Fix double setting of 'PchPwrOptEnable'

[Mario Scheithauer (Code Review)]

Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84399?usp=email )

Change subject: soc/intel/ehl/fsp_params: Fix double setting of 'PchPwrOptEnable'
......................................................................

soc/intel/ehl/fsp_params: Fix double setting of 'PchPwrOptEnable'

If real-time tuning was enabled, 'PchPwrOptEnable' was set two times. This
patch fixes the issue.

BUG=none
TEST=Enabled UPD debug output and checked 'PchPwrOptEnable' offset

Change-Id: I2f31015c1da51a4ae1b8d5226f5d7b60a6023f3d
Signed-off-by: Mario Scheithauer 
---
M src/soc/intel/elkhartlake/fsp_params.c
1 file changed, 1 insertion(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/84399/1

diff --git a/src/soc/intel/elkhartlake/fsp_params.c b/src/soc/intel/elkhartlake/fsp_params.c
index 5e1bba7..7959fca 100644
--- a/src/soc/intel/elkhartlake/fsp_params.c
+++ b/src/soc/intel/elkhartlake/fsp_params.c
@@ -324,7 +324,6 @@
    if (config->realtime_tuning_enable) {
    	params->PchPostMasterClockGating = 0;
    	params->PchPostMasterPowerGating = 0;
-		params->PchPwrOptEnable = 0;
    	params->PsfTccEnable = 1;
    	params->PmcLpmS0ixSubStateEnableMask = 0;
    	params->PchDmiAspmCtrl = 0;
@@ -333,6 +332,7 @@
    	params->D3ColdEnable = 0;
    	params->PmcOsIdleEnable = 0;
    } else {
+		params->PchPwrOptEnable = 1; /* Enable PCH DMI Power Optimizer */
    	params->PchPostMasterClockGating = 1;
    	params->PchPostMasterPowerGating = 1;
    }
@@ -471,7 +471,6 @@
    params->Custom1TurboActivationRatio = 0;
    params->Custom2TurboActivationRatio = 0;
    params->Custom3TurboActivationRatio = 0;
-	params->PchPwrOptEnable = 0x1;	//Enable PCH DMI Power Optimizer
    params->TStates = 0x0;	//Disable T state
    params->PkgCStateLimit = 0x7;	//Set C state limit to C9
    params->FastPkgCRampDisable[0] = 0x1;