Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80358?usp=email )
Change subject: arch/x86/ioapic: use uintptr_t for IOAPIC base address ......................................................................
arch/x86/ioapic: use uintptr_t for IOAPIC base address
Use uintptr_t for the IOAPIC base parameter of the various IOAPIC- related functions to avoid needing type casts in the callers. This also allows dropping the VIO_APIC_VADDR define and consistently use the IO_APIC_ADDR define instead.
Signed-off-by: Felix Held felix-coreboot@felixheld.de Change-Id: I912943e923ff092708e90138caa5e1daf269a69f Reviewed-on: https://review.coreboot.org/c/coreboot/+/80358 Reviewed-by: Elyes Haouas ehaouas@noos.fr Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Matt DeVillier matt.devillier@amd.corp-partner.google.com Reviewed-by: Jérémy Compostella jeremy.compostella@intel.com --- M src/acpi/acpi_apic.c M src/acpi/acpi_dmar.c M src/arch/x86/include/arch/ioapic.h M src/arch/x86/include/arch/smp/mpspec.h M src/arch/x86/ioapic.c M src/arch/x86/mpspec.c M src/mainboard/apple/macbook21/mptable.c M src/mainboard/asus/p2b/variants/p2b-d/mptable.c M src/mainboard/asus/p2b/variants/p2b-ds/mptable.c M src/mainboard/getac/p470/mptable.c M src/mainboard/ibase/mb899/mptable.c M src/mainboard/intel/d945gclf/mptable.c M src/mainboard/kontron/986lcd-m/mptable.c M src/mainboard/lenovo/t60/mptable.c M src/mainboard/lenovo/x60/mptable.c M src/mainboard/roda/rk886ex/mptable.c M src/northbridge/amd/pi/00730F01/northbridge.c M src/soc/amd/common/block/acpi/ivrs.c M src/soc/amd/common/block/lpc/lpc.c M src/soc/amd/common/block/root_complex/ioapic.c M src/soc/amd/stoneyridge/northbridge.c M src/soc/intel/broadwell/pch/lpc.c M src/soc/intel/common/block/lpc/lpc_lib.c M src/soc/intel/denverton_ns/lpc.c M src/soc/intel/xeon_sp/uncore_acpi.c M src/southbridge/amd/pi/hudson/sm.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/i82371eb/isa.c M src/southbridge/intel/i82801dx/lpc.c M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801ix/lpc.c M src/southbridge/intel/i82801jx/lpc.c M src/southbridge/intel/i82870/ioapic.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/lynxpoint/lpc.c 35 files changed, 89 insertions(+), 86 deletions(-)
Approvals: build bot (Jenkins): Verified Elyes Haouas: Looks good to me, but someone else must approve Jérémy Compostella: Looks good to me, but someone else must approve Matt DeVillier: Looks good to me, approved
diff --git a/src/acpi/acpi_apic.c b/src/acpi/acpi_apic.c index d6937fc..2b3402a 100644 --- a/src/acpi/acpi_apic.c +++ b/src/acpi/acpi_apic.c @@ -100,8 +100,8 @@ { static u32 gsi_base; u32 my_base; - u8 id = get_ioapic_id((void *)(uintptr_t)addr); - u8 count = ioapic_get_max_vectors((void *)(uintptr_t)addr); + u8 id = get_ioapic_id((uintptr_t)addr); + u8 count = ioapic_get_max_vectors((uintptr_t)addr);
my_base = gsi_base; gsi_base += count; diff --git a/src/acpi/acpi_dmar.c b/src/acpi/acpi_dmar.c index 9a5ebed..3853142 100644 --- a/src/acpi/acpi_dmar.c +++ b/src/acpi/acpi_dmar.c @@ -183,7 +183,7 @@ unsigned long acpi_create_dmar_ds_ioapic_from_hw(unsigned long current, u32 addr, u8 bus, u8 dev, u8 fn) { - u8 enumeration_id = get_ioapic_id((void *)(uintptr_t)addr); + u8 enumeration_id = get_ioapic_id((uintptr_t)addr); return acpi_create_dmar_ds(current, SCOPE_IOAPIC, enumeration_id, bus, dev, fn); } diff --git a/src/arch/x86/include/arch/ioapic.h b/src/arch/x86/include/arch/ioapic.h index 9dc2339..530128a 100644 --- a/src/arch/x86/include/arch/ioapic.h +++ b/src/arch/x86/include/arch/ioapic.h @@ -4,24 +4,23 @@ #define __I386_ARCH_IOAPIC_H
#define IO_APIC_ADDR 0xfec00000 -#define VIO_APIC_VADDR ((u8 *)IO_APIC_ADDR)
#ifndef __ACPI__
#include <types.h>
-u8 get_ioapic_id(void *ioapic_base); -u8 get_ioapic_version(void *ioapic_base); +u8 get_ioapic_id(uintptr_t ioapic_base); +u8 get_ioapic_version(uintptr_t ioapic_base);
-unsigned int ioapic_get_max_vectors(void *ioapic_base); -void ioapic_set_max_vectors(void *ioapic_base, int mre_count); -void ioapic_lock_max_vectors(void *ioapic_base); +unsigned int ioapic_get_max_vectors(uintptr_t ioapic_base); +void ioapic_set_max_vectors(uintptr_t ioapic_base, int mre_count); +void ioapic_lock_max_vectors(uintptr_t ioapic_base);
-void setup_ioapic(void *ioapic_base, u8 ioapic_id); -void register_new_ioapic(void *ioapic_base); -void register_new_ioapic_gsi0(void *ioapic_base); +void setup_ioapic(uintptr_t ioapic_base, u8 ioapic_id); +void register_new_ioapic(uintptr_t ioapic_base); +void register_new_ioapic_gsi0(uintptr_t ioapic_base);
-void ioapic_set_boot_config(void *ioapic_base, bool irq_on_fsb); +void ioapic_set_boot_config(uintptr_t ioapic_base, bool irq_on_fsb);
void ioapic_get_sci_pin(u8 *gsi, u8 *irq, u8 *flags); #endif diff --git a/src/arch/x86/include/arch/smp/mpspec.h b/src/arch/x86/include/arch/smp/mpspec.h index 0b5ca47..80ae7e8 100644 --- a/src/arch/x86/include/arch/smp/mpspec.h +++ b/src/arch/x86/include/arch/smp/mpspec.h @@ -6,6 +6,7 @@ #include <acpi/acpi.h> #include <device/device.h> #include <cpu/x86/lapic_def.h> +#include <types.h>
/* * Structure definitions for SMP machines following the @@ -227,7 +228,7 @@ void smp_write_processors(struct mp_config_table *mc);
/* Call smp_write_ioapic() and return IOAPIC ID field. */ -u8 smp_write_ioapic_from_hw(struct mp_config_table *mc, void *apicaddr); +u8 smp_write_ioapic_from_hw(struct mp_config_table *mc, uintptr_t apicaddr);
void smp_write_intsrc(struct mp_config_table *mc, u8 irqtype, u16 irqflag, u8 srcbus, u8 srcbusirq, diff --git a/src/arch/x86/ioapic.c b/src/arch/x86/ioapic.c index df97a50..863317f 100644 --- a/src/arch/x86/ioapic.c +++ b/src/arch/x86/ioapic.c @@ -5,6 +5,8 @@ #include <arch/ioapic.h> #include <console/console.h> #include <cpu/x86/lapic.h> +#include <inttypes.h> +#include <types.h>
#define ALL (0xff << 24) #define NONE (0) @@ -21,19 +23,19 @@ #define SMI (2 << 8) #define INT (1 << 8)
-static u32 io_apic_read(void *ioapic_base, u32 reg) +static u32 io_apic_read(uintptr_t ioapic_base, u32 reg) { - write32(ioapic_base, reg); - return read32(ioapic_base + 0x10); + write32p(ioapic_base, reg); + return read32p(ioapic_base + 0x10); }
-static void io_apic_write(void *ioapic_base, u32 reg, u32 value) +static void io_apic_write(uintptr_t ioapic_base, u32 reg, u32 value) { - write32(ioapic_base, reg); - write32(ioapic_base + 0x10, value); + write32p(ioapic_base, reg); + write32p(ioapic_base + 0x10, value); }
-static void write_vector(void *ioapic_base, u8 vector, u32 high, u32 low) +static void write_vector(uintptr_t ioapic_base, u8 vector, u32 high, u32 low) { io_apic_write(ioapic_base, vector * 2 + 0x10, low); io_apic_write(ioapic_base, vector * 2 + 0x11, high); @@ -44,7 +46,7 @@
/* Bits 23-16 of register 0x01 specify the maximum redirection entry, which * is the number of interrupts minus 1. */ -unsigned int ioapic_get_max_vectors(void *ioapic_base) +unsigned int ioapic_get_max_vectors(uintptr_t ioapic_base) { u32 reg; u8 count; @@ -63,7 +65,7 @@ /* Set maximum number of redirection entries (MRE). It is write-once register * for some chipsets, and a negative mre_count will lock it to the number * of vectors read from the register. */ -void ioapic_set_max_vectors(void *ioapic_base, int mre_count) +void ioapic_set_max_vectors(uintptr_t ioapic_base, int mre_count) { u32 reg; u8 count; @@ -77,17 +79,17 @@ io_apic_write(ioapic_base, 0x01, reg); }
-void ioapic_lock_max_vectors(void *ioapic_base) +void ioapic_lock_max_vectors(uintptr_t ioapic_base) { ioapic_set_max_vectors(ioapic_base, -1); }
-static void clear_vectors(void *ioapic_base, u8 first, u8 last) +static void clear_vectors(uintptr_t ioapic_base, u8 first, u8 last) { u32 low, high; u8 i;
- printk(BIOS_DEBUG, "IOAPIC: Clearing IOAPIC at %p\n", ioapic_base); + printk(BIOS_DEBUG, "IOAPIC: Clearing IOAPIC at %" PRIxPTR "\n", ioapic_base);
low = INT_DISABLED; high = NONE; @@ -101,7 +103,7 @@ } }
-static void route_i8259_irq0(void *ioapic_base) +static void route_i8259_irq0(uintptr_t ioapic_base) { u32 bsp_lapicid = lapicid(); u32 low, high; @@ -123,11 +125,11 @@ } }
-static void set_ioapic_id(void *ioapic_base, u8 ioapic_id) +static void set_ioapic_id(uintptr_t ioapic_base, u8 ioapic_id) { int i;
- printk(BIOS_DEBUG, "IOAPIC: Initializing IOAPIC at %p\n", + printk(BIOS_DEBUG, "IOAPIC: Initializing IOAPIC at %" PRIxPTR "\n", ioapic_base); printk(BIOS_DEBUG, "IOAPIC: ID = 0x%02x\n", ioapic_id);
@@ -141,7 +143,7 @@
}
-u8 get_ioapic_id(void *ioapic_base) +u8 get_ioapic_id(uintptr_t ioapic_base) { /* * According to 82093AA I/O ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (IOAPIC) @@ -151,12 +153,12 @@ return (io_apic_read(ioapic_base, 0x00) >> 24) & 0xff; }
-u8 get_ioapic_version(void *ioapic_base) +u8 get_ioapic_version(uintptr_t ioapic_base) { return io_apic_read(ioapic_base, 0x01) & 0xff; }
-void ioapic_set_boot_config(void *ioapic_base, bool irq_on_fsb) +void ioapic_set_boot_config(uintptr_t ioapic_base, bool irq_on_fsb) { if (irq_on_fsb) { /* @@ -173,19 +175,19 @@ } }
-void setup_ioapic(void *ioapic_base, u8 ioapic_id) +void setup_ioapic(uintptr_t ioapic_base, u8 ioapic_id) { set_ioapic_id(ioapic_base, ioapic_id); clear_vectors(ioapic_base, 0, ioapic_get_max_vectors(ioapic_base) - 1); route_i8259_irq0(ioapic_base); }
-void register_new_ioapic_gsi0(void *ioapic_base) +void register_new_ioapic_gsi0(uintptr_t ioapic_base) { setup_ioapic(ioapic_base, 0); }
-void register_new_ioapic(void *ioapic_base) +void register_new_ioapic(uintptr_t ioapic_base) { static u8 ioapic_id; ioapic_id++; diff --git a/src/arch/x86/mpspec.c b/src/arch/x86/mpspec.c index ac3fc79..f5242d3 100644 --- a/src/arch/x86/mpspec.c +++ b/src/arch/x86/mpspec.c @@ -11,8 +11,8 @@ #include <device/pci_def.h> #include <device/pci_ids.h> #include <identity.h> -#include <stdint.h> #include <string.h> +#include <types.h>
/* Initialize the specified "mc" struct with initial values. */ void mptable_init(struct mp_config_table *mc) @@ -207,7 +207,7 @@ * APIC Flags:EN, Address */ static void smp_write_ioapic(struct mp_config_table *mc, - u8 id, u8 ver, void *apicaddr) + u8 id, u8 ver, uintptr_t apicaddr) { struct mpc_config_ioapic *mpc; mpc = smp_next_mpc_entry(mc); @@ -216,11 +216,11 @@ mpc->mpc_apicid = id; mpc->mpc_apicver = ver; mpc->mpc_flags = MPC_APIC_USABLE; - mpc->mpc_apicaddr = apicaddr; + mpc->mpc_apicaddr = (void *)apicaddr; smp_add_mpc_entry(mc, sizeof(*mpc)); }
-u8 smp_write_ioapic_from_hw(struct mp_config_table *mc, void *apicaddr) +u8 smp_write_ioapic_from_hw(struct mp_config_table *mc, uintptr_t apicaddr) { u8 id = get_ioapic_id(apicaddr); u8 ver = get_ioapic_version(apicaddr); diff --git a/src/mainboard/apple/macbook21/mptable.c b/src/mainboard/apple/macbook21/mptable.c index 823c856..fcf46a2 100644 --- a/src/mainboard/apple/macbook21/mptable.c +++ b/src/mainboard/apple/macbook21/mptable.c @@ -18,7 +18,7 @@ mptable_write_buses(mc, NULL, &isa_bus);
/* I/O APICs: APIC ID Version State Address */ - u8 ioapic_id = smp_write_ioapic_from_hw(mc, VIO_APIC_VADDR); + u8 ioapic_id = smp_write_ioapic_from_hw(mc, IO_APIC_ADDR);
/* Legacy Interrupts */ mptable_add_isa_interrupts(mc, isa_bus, ioapic_id, 0); diff --git a/src/mainboard/asus/p2b/variants/p2b-d/mptable.c b/src/mainboard/asus/p2b/variants/p2b-d/mptable.c index 7536077..e6b5459 100644 --- a/src/mainboard/asus/p2b/variants/p2b-d/mptable.c +++ b/src/mainboard/asus/p2b/variants/p2b-d/mptable.c @@ -17,7 +17,7 @@ mptable_write_buses(mc, NULL, &isa_bus);
/* External Intel 82093AA IOAPIC. */ - u8 ioapic_id = smp_write_ioapic_from_hw(mc, VIO_APIC_VADDR); + u8 ioapic_id = smp_write_ioapic_from_hw(mc, IO_APIC_ADDR);
/* Legacy Interrupts */ mptable_add_isa_interrupts(mc, isa_bus, ioapic_id, 0); diff --git a/src/mainboard/asus/p2b/variants/p2b-ds/mptable.c b/src/mainboard/asus/p2b/variants/p2b-ds/mptable.c index 2c22ce2..f06fc60 100644 --- a/src/mainboard/asus/p2b/variants/p2b-ds/mptable.c +++ b/src/mainboard/asus/p2b/variants/p2b-ds/mptable.c @@ -17,7 +17,7 @@ mptable_write_buses(mc, NULL, &isa_bus);
/* External Intel 82093AA IOAPIC. */ - u8 ioapic_id = smp_write_ioapic_from_hw(mc, VIO_APIC_VADDR); + u8 ioapic_id = smp_write_ioapic_from_hw(mc, IO_APIC_ADDR);
/* Legacy Interrupts */ mptable_add_isa_interrupts(mc, isa_bus, ioapic_id, 0); diff --git a/src/mainboard/getac/p470/mptable.c b/src/mainboard/getac/p470/mptable.c index a85b519..d7a4af6 100644 --- a/src/mainboard/getac/p470/mptable.c +++ b/src/mainboard/getac/p470/mptable.c @@ -18,7 +18,7 @@ mptable_write_buses(mc, NULL, &isa_bus);
/* I/O APICs: APIC ID Version State Address */ - u8 ioapic_id = smp_write_ioapic_from_hw(mc, VIO_APIC_VADDR); + u8 ioapic_id = smp_write_ioapic_from_hw(mc, IO_APIC_ADDR);
/* Legacy Interrupts */ mptable_add_isa_interrupts(mc, isa_bus, ioapic_id, 0); diff --git a/src/mainboard/ibase/mb899/mptable.c b/src/mainboard/ibase/mb899/mptable.c index a9ad7c7..bb43796 100644 --- a/src/mainboard/ibase/mb899/mptable.c +++ b/src/mainboard/ibase/mb899/mptable.c @@ -37,7 +37,7 @@ mptable_write_buses(mc, NULL, &isa_bus);
/* I/O APICs: APIC ID Version State Address */ - u8 ioapic_id = smp_write_ioapic_from_hw(mc, VIO_APIC_VADDR); + u8 ioapic_id = smp_write_ioapic_from_hw(mc, IO_APIC_ADDR);
/* Legacy Interrupts */
diff --git a/src/mainboard/intel/d945gclf/mptable.c b/src/mainboard/intel/d945gclf/mptable.c index 8dde3a7..7ab47b4 100644 --- a/src/mainboard/intel/d945gclf/mptable.c +++ b/src/mainboard/intel/d945gclf/mptable.c @@ -18,7 +18,7 @@ mptable_write_buses(mc, NULL, &isa_bus);
/* I/O APICs: APIC ID Version State Address */ - u8 ioapic_id = smp_write_ioapic_from_hw(mc, VIO_APIC_VADDR); + u8 ioapic_id = smp_write_ioapic_from_hw(mc, IO_APIC_ADDR);
/* Legacy Interrupts */
diff --git a/src/mainboard/kontron/986lcd-m/mptable.c b/src/mainboard/kontron/986lcd-m/mptable.c index b0bfbe7..5ee3288 100644 --- a/src/mainboard/kontron/986lcd-m/mptable.c +++ b/src/mainboard/kontron/986lcd-m/mptable.c @@ -33,7 +33,7 @@ mptable_write_buses(mc, NULL, &isa_bus);
/* I/O APICs: APIC ID Version State Address */ - u8 ioapic_id = smp_write_ioapic_from_hw(mc, VIO_APIC_VADDR); + u8 ioapic_id = smp_write_ioapic_from_hw(mc, IO_APIC_ADDR);
/* Legacy Interrupts */ mptable_add_isa_interrupts(mc, isa_bus, ioapic_id, 0); diff --git a/src/mainboard/lenovo/t60/mptable.c b/src/mainboard/lenovo/t60/mptable.c index b4231d3..f640085 100644 --- a/src/mainboard/lenovo/t60/mptable.c +++ b/src/mainboard/lenovo/t60/mptable.c @@ -18,7 +18,7 @@ mptable_write_buses(mc, NULL, &isa_bus);
/* I/O APICs: APIC ID Version State Address */ - u8 ioapic_id = smp_write_ioapic_from_hw(mc, VIO_APIC_VADDR); + u8 ioapic_id = smp_write_ioapic_from_hw(mc, IO_APIC_ADDR);
/* Legacy Interrupts */ mptable_add_isa_interrupts(mc, isa_bus, ioapic_id, 0); diff --git a/src/mainboard/lenovo/x60/mptable.c b/src/mainboard/lenovo/x60/mptable.c index 8e972a7..73e9c1b 100644 --- a/src/mainboard/lenovo/x60/mptable.c +++ b/src/mainboard/lenovo/x60/mptable.c @@ -18,7 +18,7 @@ mptable_write_buses(mc, NULL, &isa_bus);
/* I/O APICs: APIC ID Version State Address */ - u8 ioapic_id = smp_write_ioapic_from_hw(mc, VIO_APIC_VADDR); + u8 ioapic_id = smp_write_ioapic_from_hw(mc, IO_APIC_ADDR);
/* Legacy Interrupts */ mptable_add_isa_interrupts(mc, isa_bus, ioapic_id, 0); diff --git a/src/mainboard/roda/rk886ex/mptable.c b/src/mainboard/roda/rk886ex/mptable.c index d7bc09e..3ce1cbc 100644 --- a/src/mainboard/roda/rk886ex/mptable.c +++ b/src/mainboard/roda/rk886ex/mptable.c @@ -18,7 +18,7 @@ mptable_write_buses(mc, NULL, &isa_bus);
/* I/O APICs: APIC ID Version State Address */ - u8 ioapic_id = smp_write_ioapic_from_hw(mc, VIO_APIC_VADDR); + u8 ioapic_id = smp_write_ioapic_from_hw(mc, IO_APIC_ADDR);
/* Legacy Interrupts */ mptable_add_isa_interrupts(mc, isa_bus, ioapic_id, 0); diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index bc5439d..430eeef 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -87,7 +87,7 @@
static void northbridge_init(struct device *dev) { - register_new_ioapic((u8 *)IO_APIC2_ADDR); + register_new_ioapic(IO_APIC2_ADDR); }
static unsigned long acpi_fill_hest(acpi_hest_t *hest) @@ -119,7 +119,7 @@ ivhd_ioapic->dte_setting = IVHD_DTE_LINT_1_PASS | IVHD_DTE_LINT_0_PASS | IVHD_DTE_SYS_MGT_NO_TRANS | IVHD_DTE_NMI_PASS | IVHD_DTE_EXT_INT_PASS | IVHD_DTE_INIT_PASS; - ivhd_ioapic->handle = get_ioapic_id(VIO_APIC_VADDR); + ivhd_ioapic->handle = get_ioapic_id(IO_APIC_ADDR); ivhd_ioapic->source_dev_id = PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC); ivhd_ioapic->variety = IVHD_SPECIAL_DEV_IOAPIC; current += sizeof(ivrs_ivhd_special_t); @@ -128,7 +128,7 @@ ivhd_ioapic->type = IVHD_DEV_8_BYTE_EXT_SPECIAL_DEV; ivhd_ioapic->reserved = 0x0000; ivhd_ioapic->dte_setting = 0x00; - ivhd_ioapic->handle = get_ioapic_id((u8 *)IO_APIC2_ADDR); + ivhd_ioapic->handle = get_ioapic_id(IO_APIC2_ADDR); ivhd_ioapic->source_dev_id = PCI_DEVFN(0, 1); ivhd_ioapic->variety = IVHD_SPECIAL_DEV_IOAPIC; current += sizeof(ivrs_ivhd_special_t); diff --git a/src/soc/amd/common/block/acpi/ivrs.c b/src/soc/amd/common/block/acpi/ivrs.c index bd52d7c..74c5c39 100644 --- a/src/soc/amd/common/block/acpi/ivrs.c +++ b/src/soc/amd/common/block/acpi/ivrs.c @@ -16,7 +16,7 @@ #include <soc/iomap.h> #include <soc/pci_devs.h>
-static unsigned long acpi_fill_ivrs_ioapic(unsigned long current, void *ioapic_base, +static unsigned long acpi_fill_ivrs_ioapic(unsigned long current, uintptr_t ioapic_base, uint16_t src_devid, uint8_t dte_setting) { ivrs_ivhd_special_t *ivhd_ioapic = (ivrs_ivhd_special_t *)current; @@ -182,7 +182,7 @@ res = probe_resource(dev, IOMMU_IOAPIC_IDX); if (res) { /* Describe IOAPIC associated with the IOMMU */ - current = acpi_fill_ivrs_ioapic(current, (u8 *)(uintptr_t)res->base, + current = acpi_fill_ivrs_ioapic(current, (uintptr_t)res->base, PCI_DEVFN(0, 1) | (dev->downstream->secondary << 8), 0); }
@@ -191,7 +191,7 @@ /* Describe HPET */ current = ivhd_describe_hpet(current, 0x00, SMBUS_DEVFN); /* Describe FCH IOAPICs */ - current = acpi_fill_ivrs_ioapic(current, VIO_APIC_VADDR, + current = acpi_fill_ivrs_ioapic(current, IO_APIC_ADDR, SMBUS_DEVFN, dte_setting); }
diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c index a90fc3e..2392d5f 100644 --- a/src/soc/amd/common/block/lpc/lpc.c +++ b/src/soc/amd/common/block/lpc/lpc.c @@ -45,7 +45,7 @@ static void fch_ioapic_init(void) { fch_enable_ioapic_decode(); - register_new_ioapic_gsi0(VIO_APIC_VADDR); + register_new_ioapic_gsi0(IO_APIC_ADDR); }
static void lpc_init(struct device *dev) diff --git a/src/soc/amd/common/block/root_complex/ioapic.c b/src/soc/amd/common/block/root_complex/ioapic.c index cdeb532..e183428 100644 --- a/src/soc/amd/common/block/root_complex/ioapic.c +++ b/src/soc/amd/common/block/root_complex/ioapic.c @@ -13,5 +13,5 @@ if (!res) return;
- register_new_ioapic((void *)(uintptr_t)res->base); + register_new_ioapic((uintptr_t)res->base); } diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index a92c3b5..b51601b 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -73,7 +73,7 @@
static void northbridge_init(struct device *dev) { - register_new_ioapic((u8 *)IO_APIC2_ADDR); + register_new_ioapic(IO_APIC2_ADDR); }
/* Used by _SB.PCI0._CRS */ diff --git a/src/soc/intel/broadwell/pch/lpc.c b/src/soc/intel/broadwell/pch/lpc.c index 9aaca21..ecd66fa 100644 --- a/src/soc/intel/broadwell/pch/lpc.c +++ b/src/soc/intel/broadwell/pch/lpc.c @@ -31,9 +31,9 @@
/* affirm full set of redirection table entries ("write once") */ /* PCH-LP has 40 redirection entries */ - ioapic_set_max_vectors(VIO_APIC_VADDR, 40); + ioapic_set_max_vectors(IO_APIC_ADDR, 40);
- register_new_ioapic_gsi0(VIO_APIC_VADDR); + register_new_ioapic_gsi0(IO_APIC_ADDR); }
#define ACPI_SCI_IRQ 9 diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c index ed76049..9a7165b 100644 --- a/src/soc/intel/common/block/lpc/lpc_lib.c +++ b/src/soc/intel/common/block/lpc/lpc_lib.c @@ -395,9 +395,9 @@ void pch_enable_ioapic(void) { /* affirm full set of redirection table entries ("write once") */ - ioapic_set_max_vectors(VIO_APIC_VADDR, PCH_REDIR_ETR); + ioapic_set_max_vectors(IO_APIC_ADDR, PCH_REDIR_ETR);
- register_new_ioapic_gsi0((void *)IO_APIC_ADDR); + register_new_ioapic_gsi0(IO_APIC_ADDR); }
static const uint8_t pch_interrupt_routing[PIRQ_COUNT] = { diff --git a/src/soc/intel/denverton_ns/lpc.c b/src/soc/intel/denverton_ns/lpc.c index ae923d7..7dc971e 100644 --- a/src/soc/intel/denverton_ns/lpc.c +++ b/src/soc/intel/denverton_ns/lpc.c @@ -32,9 +32,9 @@ static void pch_enable_ioapic(struct device *dev) { /* affirm full set of redirection table entries ("write once") */ - ioapic_set_max_vectors(VIO_APIC_VADDR, PCH_REDIR_ETR); + ioapic_set_max_vectors(IO_APIC_ADDR, PCH_REDIR_ETR);
- register_new_ioapic_gsi0((void *)IO_APIC_ADDR); + register_new_ioapic_gsi0(IO_APIC_ADDR); }
/* interrupt router lookup for internal devices */ diff --git a/src/soc/intel/xeon_sp/uncore_acpi.c b/src/soc/intel/xeon_sp/uncore_acpi.c index 5ee9087..b4856120 100644 --- a/src/soc/intel/xeon_sp/uncore_acpi.c +++ b/src/soc/intel/xeon_sp/uncore_acpi.c @@ -283,7 +283,7 @@ if (socket == 0 && stack == IioStack0) { union p2sb_bdf ioapic_bdf = p2sb_get_ioapic_bdf(); printk(BIOS_DEBUG, " [IOAPIC Device] Enumeration ID: 0x%x, PCI Bus Number: 0x%x, " - "PCI Path: 0x%x, 0x%x\n", get_ioapic_id(VIO_APIC_VADDR), ioapic_bdf.bus, + "PCI Path: 0x%x, 0x%x\n", get_ioapic_id(IO_APIC_ADDR), ioapic_bdf.bus, ioapic_bdf.dev, ioapic_bdf.fn); current += acpi_create_dmar_ds_ioapic_from_hw(current, IO_APIC_ADDR, ioapic_bdf.bus, ioapic_bdf.dev, ioapic_bdf.fn); diff --git a/src/southbridge/amd/pi/hudson/sm.c b/src/southbridge/amd/pi/hudson/sm.c index 593f548..70e4985 100644 --- a/src/southbridge/amd/pi/hudson/sm.c +++ b/src/southbridge/amd/pi/hudson/sm.c @@ -28,7 +28,7 @@
static void sm_init(struct device *dev) { - register_new_ioapic_gsi0(VIO_APIC_VADDR); + register_new_ioapic_gsi0(IO_APIC_ADDR); }
static int lsmbus_recv_byte(struct device *dev) diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 69c9d44..67d883a 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -41,9 +41,9 @@ PCH_IOAPIC_PCI_BUS << 8 | PCH_IOAPIC_PCI_SLOT << 3);
/* affirm full set of redirection table entries ("write once") */ - ioapic_lock_max_vectors(VIO_APIC_VADDR); + ioapic_lock_max_vectors(IO_APIC_ADDR);
- register_new_ioapic_gsi0(VIO_APIC_VADDR); + register_new_ioapic_gsi0(IO_APIC_ADDR); }
static void pch_enable_serial_irqs(struct device *dev) diff --git a/src/southbridge/intel/i82371eb/isa.c b/src/southbridge/intel/i82371eb/isa.c index 9d03de0..692fd8b 100644 --- a/src/southbridge/intel/i82371eb/isa.c +++ b/src/southbridge/intel/i82371eb/isa.c @@ -61,8 +61,8 @@ pci_write_config16(dev, XBCS, reg16);
/* Set and verify the IOAPIC ID. */ - setup_ioapic(VIO_APIC_VADDR, ioapic_id); - if (ioapic_id != get_ioapic_id(VIO_APIC_VADDR)) + setup_ioapic(IO_APIC_ADDR, ioapic_id); + if (ioapic_id != get_ioapic_id(IO_APIC_ADDR)) die("IOAPIC error!\n"); } } diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c index d914335..c8b0760 100644 --- a/src/southbridge/intel/i82801dx/lpc.c +++ b/src/southbridge/intel/i82801dx/lpc.c @@ -39,9 +39,9 @@ pci_write_config32(dev, GEN_CNTL, reg32); printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32);
- register_new_ioapic_gsi0(VIO_APIC_VADDR); + register_new_ioapic_gsi0(IO_APIC_ADDR);
- ioapic_set_boot_config(VIO_APIC_VADDR, true); + ioapic_set_boot_config(IO_APIC_ADDR, true); }
static void i82801dx_enable_serial_irqs(struct device *dev) diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 28cde3e..a04b4b9 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -34,7 +34,7 @@ */ static void i82801gx_enable_ioapic(struct device *dev) { - register_new_ioapic_gsi0(VIO_APIC_VADDR); + register_new_ioapic_gsi0(IO_APIC_ADDR); }
static void i82801gx_enable_serial_irqs(struct device *dev) diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index 91b7456..0adc1b9 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -34,9 +34,9 @@ RCBA8(0x31ff);
/* Lock maximum redirection entries (MRE), R/WO register. */ - ioapic_lock_max_vectors(VIO_APIC_VADDR); + ioapic_lock_max_vectors(IO_APIC_ADDR);
- register_new_ioapic_gsi0(VIO_APIC_VADDR); + register_new_ioapic_gsi0(IO_APIC_ADDR); }
static void i82801ix_enable_serial_irqs(struct device *dev) diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index 7cff33a..0a3e26f 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -35,9 +35,9 @@ RCBA8(0x31ff);
/* Lock maximum redirection entries (MRE), R/WO register. */ - ioapic_lock_max_vectors(VIO_APIC_VADDR); + ioapic_lock_max_vectors(IO_APIC_ADDR);
- register_new_ioapic_gsi0(VIO_APIC_VADDR); + register_new_ioapic_gsi0(IO_APIC_ADDR); }
static void i82801jx_enable_serial_irqs(struct device *dev) diff --git a/src/southbridge/intel/i82870/ioapic.c b/src/southbridge/intel/i82870/ioapic.c index f6a4ac0..4a25f6b 100644 --- a/src/southbridge/intel/i82870/ioapic.c +++ b/src/southbridge/intel/i82870/ioapic.c @@ -6,6 +6,7 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <assert.h> +#include <types.h> #include "82870.h"
static void p64h2_ioapic_enable(struct device *dev) @@ -27,17 +28,17 @@ */ static void p64h2_ioapic_init(struct device *dev) { - uint32_t memoryBase; + uintptr_t memoryBase;
// Read the MBAR address for setting up the IOAPIC in memory space // NOTE: this address was assigned during enumeration of the bus
- memoryBase = pci_read_config32(dev, PCI_BASE_ADDRESS_0); + memoryBase = (uintptr_t)pci_read_config32(dev, PCI_BASE_ADDRESS_0);
- register_new_ioapic((void *)memoryBase); + register_new_ioapic(memoryBase);
// Use Processor System Bus to deliver interrupts - ioapic_set_boot_config((void *)memoryBase, true); + ioapic_set_boot_config(memoryBase, true); }
static struct device_operations ioapic_ops = { diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 7d85883..93dc387 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -33,9 +33,9 @@ static void pch_enable_ioapic(struct device *dev) { /* affirm full set of redirection table entries ("write once") */ - ioapic_lock_max_vectors(VIO_APIC_VADDR); + ioapic_lock_max_vectors(IO_APIC_ADDR);
- register_new_ioapic_gsi0(VIO_APIC_VADDR); + register_new_ioapic_gsi0(IO_APIC_ADDR); }
static void pch_enable_serial_irqs(struct device *dev) diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index e44d9a8..93b7423 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -38,11 +38,11 @@ /* affirm full set of redirection table entries ("write once") */ /* PCH-LP has 40 redirection entries */ if (pch_is_lp()) - ioapic_set_max_vectors(VIO_APIC_VADDR, 40); + ioapic_set_max_vectors(IO_APIC_ADDR, 40); else - ioapic_lock_max_vectors(VIO_APIC_VADDR); + ioapic_lock_max_vectors(IO_APIC_ADDR);
- register_new_ioapic_gsi0(VIO_APIC_VADDR); + register_new_ioapic_gsi0(IO_APIC_ADDR); }
static void pch_enable_serial_irqs(struct device *dev)