[S] Change in coreboot[main]: soc/intel/snowridge: add CPU and PCIe definitions for SNR

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Attention is currently required from: Shuo Liu, [e-mail].

Hello Jérémy Compostella, Shuo Liu, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/83314?usp=email

to look at the new patch set (#2).

The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)

Change subject: soc/intel/snowridge: add CPU and PCIe definitions for SNR
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soc/intel/snowridge: add CPU and PCIe definitions for SNR

Change-Id: I3f5d612765bbe9adffe0b6c7a4151f32b33e88b4
Signed-off-by: Yuchi Chen 
---
M src/include/cpu/intel/cpu_ids.h
M src/include/device/pci_ids.h
M src/soc/intel/common/block/cpu/mp_init.c
M src/soc/intel/common/block/lpc/lpc.c
M src/soc/intel/common/block/p2sb/p2sb.c
M src/soc/intel/common/block/systemagent/systemagent.c
M src/soc/intel/common/block/xhci/xhci.c
7 files changed, 22 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/83314/2