Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59008 )
Change subject: mb/google,samsung: Drop init_bootmode_straps() ......................................................................
mb/google,samsung: Drop init_bootmode_straps()
Change-Id: Idcaf30c622bf5dc0f1295f2639c656086d01ff7e Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/59008 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Julius Werner jwerner@chromium.org --- M src/include/bootmode.h M src/mainboard/google/beltino/chromeos.c M src/mainboard/google/jecht/chromeos.c D src/mainboard/google/jecht/romstage.c M src/mainboard/samsung/lumpy/chromeos.c M src/mainboard/samsung/lumpy/early_init.c M src/mainboard/samsung/stumpy/chromeos.c M src/mainboard/samsung/stumpy/early_init.c M src/northbridge/intel/sandybridge/romstage.c M src/soc/intel/broadwell/pch/Makefile.inc 10 files changed, 9 insertions(+), 173 deletions(-)
Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved
diff --git a/src/include/bootmode.h b/src/include/bootmode.h index 12c9f58..0871f8f 100644 --- a/src/include/bootmode.h +++ b/src/include/bootmode.h @@ -6,7 +6,6 @@ #include <stdbool.h>
/* functions implemented per mainboard: */ -void init_bootmode_straps(void); int get_write_protect_state(void); int get_recovery_mode_switch(void); int get_recovery_mode_retrain_switch(void); diff --git a/src/mainboard/google/beltino/chromeos.c b/src/mainboard/google/beltino/chromeos.c index 227e595..0e01895 100644 --- a/src/mainboard/google/beltino/chromeos.c +++ b/src/mainboard/google/beltino/chromeos.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#include <device/pci_ops.h> #include <bootmode.h> #include <boot/coreboot_tables.h> #include <device/device.h> @@ -10,9 +9,6 @@ #include <vendorcode/google/chromeos/chromeos.h> #include "onboard.h"
-#define FLAG_SPI_WP 0 -#define FLAG_REC_MODE 1 - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -25,44 +21,14 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); }
-static bool raw_write_protect_state(void) +int get_write_protect_state(void) { return get_gpio(GPIO_SPI_WP); }
-static bool raw_recovery_mode_switch(void) -{ - return !get_gpio(GPIO_REC_MODE); -} - -int get_write_protect_state(void) -{ - const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); - return (pci_s_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1; -} - int get_recovery_mode_switch(void) { - const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); - return (pci_s_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1; -} - -void init_bootmode_straps(void) -{ - u32 flags = 0; - const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); - - /* Write Protect: GPIO58 = GPIO_SPI_WP, active high */ - if (raw_write_protect_state()) - flags |= (1 << FLAG_SPI_WP); - - /* Recovery: GPIO12 = RECOVERY_L, active low */ - if (raw_recovery_mode_switch()) - flags |= (1 << FLAG_REC_MODE); - - /* Developer: Virtual */ - - pci_s_write_config32(dev, SATA_SP, flags); + return !get_gpio(GPIO_REC_MODE); }
static const struct cros_gpio cros_gpios[] = { diff --git a/src/mainboard/google/jecht/chromeos.c b/src/mainboard/google/jecht/chromeos.c index d8ecb4e..563e32b 100644 --- a/src/mainboard/google/jecht/chromeos.c +++ b/src/mainboard/google/jecht/chromeos.c @@ -6,15 +6,10 @@ #include <device/device.h> #include <types.h> #include <vendorcode/google/chromeos/chromeos.h> -#include <ec/google/chromeec/ec.h> #include <soc/chromeos.h> -#include <soc/sata.h> #include <southbridge/intel/lynxpoint/lp_gpio.h> #include "onboard.h"
-#define FLAG_SPI_WP 0 -#define FLAG_REC_MODE 1 - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -27,44 +22,14 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); }
-static bool raw_write_protect_state(void) +int get_write_protect_state(void) { return get_gpio(GPIO_SPI_WP); }
-static bool raw_recovery_mode_switch(void) -{ - return !get_gpio(GPIO_REC_MODE); -} - -int get_write_protect_state(void) -{ - const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); - return (pci_s_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1; -} - int get_recovery_mode_switch(void) { - const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); - return (pci_s_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1; -} - -void init_bootmode_straps(void) -{ - u32 flags = 0; - const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); - - /* Write Protect: GPIO58 = GPIO_SPI_WP, active high */ - if (raw_write_protect_state()) - flags |= (1 << FLAG_SPI_WP); - - /* Recovery: GPIO12 = RECOVERY_L, active low */ - if (raw_recovery_mode_switch()) - flags |= (1 << FLAG_REC_MODE); - - /* Developer: Virtual */ - - pci_s_write_config32(dev, SATA_SP, flags); + return !get_gpio(GPIO_REC_MODE); }
static const struct cros_gpio cros_gpios[] = { diff --git a/src/mainboard/google/jecht/romstage.c b/src/mainboard/google/jecht/romstage.c deleted file mode 100644 index 5c978ba..0000000 --- a/src/mainboard/google/jecht/romstage.c +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <bootmode.h> -#include <console/console.h> -#include <ec/google/chromeec/ec.h> -#include <soc/pei_data.h> -#include <soc/pei_wrapper.h> -#include <soc/romstage.h> -#include <superio/ite/common/ite.h> -#include <superio/ite/it8772f/it8772f.h> -#include "onboard.h" - -void mainboard_post_raminit(const int s3resume) -{ - if (CONFIG(CHROMEOS)) - init_bootmode_straps(); -} diff --git a/src/mainboard/samsung/lumpy/chromeos.c b/src/mainboard/samsung/lumpy/chromeos.c index ba5eabe..7761c69 100644 --- a/src/mainboard/samsung/lumpy/chromeos.c +++ b/src/mainboard/samsung/lumpy/chromeos.c @@ -4,16 +4,12 @@ #include <boot/coreboot_tables.h> #include <device/pci_ops.h> #include <device/device.h> -#include <northbridge/intel/sandybridge/sandybridge.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> #include <types.h> #include <vendorcode/google/chromeos/chromeos.h> #include "onboard.h"
-#define FLAG_SPI_WP 0 -#define FLAG_REC_MODE 1 - #include "ec.h" #include <ec/smsc/mec1308/ec.h>
@@ -36,12 +32,12 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); }
-static bool raw_write_protect_state(void) +int get_write_protect_state(void) { return get_gpio(GPIO_SPI_WP); }
-static bool raw_recovery_mode_switch(void) +int get_recovery_mode_switch(void) { return !get_gpio(GPIO_REC_MODE); } @@ -58,33 +54,6 @@ return (gen_pmcon_1 >> 9) & 1; }
-int get_write_protect_state(void) -{ - const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); - return (pci_s_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1; -} - -int get_recovery_mode_switch(void) -{ - const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); - return (pci_s_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1; -} - -void init_bootmode_straps(void) -{ - u32 flags = 0; - const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); - - /* Write Protect: GPIO24 = KBC3_SPI_WP#, active high */ - if (raw_write_protect_state()) - flags |= (1 << FLAG_SPI_WP); - /* Recovery: GPIO42 = CHP3_REC_MODE#, active low */ - if (raw_recovery_mode_switch()) - flags |= (1 << FLAG_REC_MODE); - - pci_s_write_config32(dev, SATA_SP, flags); -} - static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), diff --git a/src/mainboard/samsung/lumpy/early_init.c b/src/mainboard/samsung/lumpy/early_init.c index 26c8826..fd0f944 100644 --- a/src/mainboard/samsung/lumpy/early_init.c +++ b/src/mainboard/samsung/lumpy/early_init.c @@ -182,11 +182,6 @@ read_spd(&spd[0], 0x50, id_only); }
-void mainboard_early_init(int s3resume) -{ - init_bootmode_straps(); -} - int mainboard_should_reset_usb(int s3resume) { return !s3resume; diff --git a/src/mainboard/samsung/stumpy/chromeos.c b/src/mainboard/samsung/stumpy/chromeos.c index 61782f8..739b577 100644 --- a/src/mainboard/samsung/stumpy/chromeos.c +++ b/src/mainboard/samsung/stumpy/chromeos.c @@ -10,9 +10,6 @@ #include <vendorcode/google/chromeos/chromeos.h> #include "onboard.h"
-#define FLAG_SPI_WP 0 -#define FLAG_REC_MODE 1 - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -33,12 +30,12 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); }
-static bool raw_write_protect_state(void) +int get_write_protect_state(void) { return get_gpio(GPIO_SPI_WP); }
-static bool raw_recovery_mode_switch(void) +int get_recovery_mode_switch(void) { return !get_gpio(GPIO_REC_MODE); } @@ -50,34 +47,6 @@ return (gen_pmcon_1 >> 9) & 1; }
-int get_write_protect_state(void) -{ - const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); - return (pci_s_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1; -} - -int get_recovery_mode_switch(void) -{ - const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); - return (pci_s_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1; -} - -void init_bootmode_straps(void) -{ - u32 flags = 0; - const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); - - /* Write Protect: GPIO68 = CHP3_SPI_WP, active high */ - if (raw_write_protect_state()) - flags |= (1 << FLAG_SPI_WP); - - /* Recovery: GPIO42 = CHP3_REC_MODE#, active low */ - if (raw_recovery_mode_switch()) - flags |= (1 << FLAG_REC_MODE); - - pci_s_write_config32(dev, SATA_SP, flags); -} - static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), diff --git a/src/mainboard/samsung/stumpy/early_init.c b/src/mainboard/samsung/stumpy/early_init.c index dfb1f4d0..97f656a 100644 --- a/src/mainboard/samsung/stumpy/early_init.c +++ b/src/mainboard/samsung/stumpy/early_init.c @@ -164,11 +164,6 @@ { 1, 0, 5 }, /* P13: Back port (OC5) */ };
-void mainboard_early_init(int s3resume) -{ - init_bootmode_straps(); -} - int mainboard_should_reset_usb(int s3resume) { if (s3resume) { diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index a6f626a..1b6e744 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -16,10 +16,6 @@ #include <southbridge/intel/common/pmclib.h> #include <elog.h>
-__weak void mainboard_early_init(int s3_resume) -{ -} - __weak void mainboard_late_rcba_config(void) { } @@ -71,8 +67,6 @@
post_code(0x38);
- mainboard_early_init(s3resume); - post_code(0x39);
if (CONFIG(INTEL_TXT)) { diff --git a/src/soc/intel/broadwell/pch/Makefile.inc b/src/soc/intel/broadwell/pch/Makefile.inc index 1afa92b..5bd09ea 100644 --- a/src/soc/intel/broadwell/pch/Makefile.inc +++ b/src/soc/intel/broadwell/pch/Makefile.inc @@ -6,6 +6,7 @@ ramstage-y += finalize.c ramstage-y += ../../../../southbridge/intel/lynxpoint/lp_gpio.c romstage-y += ../../../../southbridge/intel/lynxpoint/lp_gpio.c +verstage-y += ../../../../southbridge/intel/lynxpoint/lp_gpio.c smm-y += ../../../../southbridge/intel/lynxpoint/lp_gpio.c ramstage-y += hda.c ramstage-y += ../../../../southbridge/intel/lynxpoint/hda_verb.c
-
Kyösti Mälkki (Code Review)