Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Angel Pons, Nick Vaccaro. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62838 )
Change subject: soc/intel/common/block/cpu: Enable ROM caching in ramstage ......................................................................
Patch Set 1:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62838/comment/1ff3231c_beb42056 PS1, Line 9: This patch ensures to have `BIOS region` and `extended BIOS` region is : cached if the boot device is memory mapped Maybe:
Cache the BIOS region and extendend BIOS region if the boot device is memory mapped, which …
https://review.coreboot.org/c/coreboot/+/62838/comment/0e6e087d_ee440c12 PS1, Line 9: This patch ensures to have `BIOS region` and `extended BIOS` region is : cached if the boot device is memory mapped, which is mostly the case : with Intel SoC platform. Why should this be done? Lower boot time?
https://review.coreboot.org/c/coreboot/+/62838/comment/2ae1a277_0cda4883 PS1, Line 12: Tested on what device?
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Paul Menzel (Code Review)