Change in ...coreboot[master]: soc/intel/common/../pcie: Fix 'unsigned int' to bare use of 'unsigned'

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31913

Change subject: soc/intel/common/../pcie: Fix 'unsigned int' to bare use of 'unsigned'
......................................................................

soc/intel/common/../pcie: Fix 'unsigned int' to bare use of 'unsigned'

Change-Id: Iee09b601045d7785a0977a4f7ed7385b1d311044
Signed-off-by: Subrata Banik 
---
M src/soc/intel/common/block/pcie/pcie.c
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/31913/1

diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c
index 0a5e1bf..8295765 100644
--- a/src/soc/intel/common/block/pcie/pcie.c
+++ b/src/soc/intel/common/block/pcie/pcie.c
@@ -73,7 +73,7 @@
 }

static void pcie_dev_set_subsystem(struct device *dev,
-		unsigned vendor, unsigned device)
+		unsigned int vendor, unsigned int device)
 {
    pci_write_config32(dev, PCIE_SUBSYSTEM_VENDOR_ID,
    		((device & 0xffff) << 16) | (vendor & 0xffff));

[Lijian Zhao (Code Review)]

Lijian Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31913 )

Change subject: soc/intel/common/../pcie: Fix 'unsigned int' to bare use of 'unsigned'
......................................................................

Patch Set 1: Code-Review+2

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31913 )

Change subject: soc/intel/common/../pcie: Fix 'unsigned int' to bare use of 'unsigned'
......................................................................

Patch Set 1:

The change is correct, but when you come across these please fix the entire tree with one bulk run. Eventually someone has to do that, it would be nice if not all of that was upto volunteering contributors.

And for this particular set_subsystem(), maybe there is one standard case where one just writes these PCI config registers without any locking involved; that one should be promoted to globally available function and the dozens(?) of copies removed.

Change in ...coreboot[master]: Fix 'unsigned int' to bare use of 'unsigned'

[Subrata Banik (Code Review)]

Hello Kyösti Mälkki, Patrick Rudolph, Shelley Chen, Philipp Deppenwiese, Lijian Zhao, build bot (Jenkins), Furquan Shaikh,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/31913

to look at the new patch set (#2).

Change subject: Fix 'unsigned int' to bare use of 'unsigned'
......................................................................

Fix 'unsigned int' to bare use of 'unsigned'

Change-Id: Iee09b601045d7785a0977a4f7ed7385b1d311044
Signed-off-by: Subrata Banik 
---
M src/northbridge/amd/agesa/family12/northbridge.c
M src/northbridge/amd/agesa/family14/northbridge.c
M src/northbridge/amd/agesa/family15tn/northbridge.c
M src/northbridge/amd/agesa/family16kb/northbridge.c
M src/northbridge/amd/amdk8/reset_test.c
M src/northbridge/amd/pi/00630F01/northbridge.c
M src/northbridge/amd/pi/00660F01/northbridge.c
M src/northbridge/amd/pi/00730F01/northbridge.c
M src/northbridge/intel/sandybridge/gma.c
M src/northbridge/intel/sandybridge/raminit_common.c
M src/soc/intel/common/block/pcie/pcie.c
11 files changed, 125 insertions(+), 124 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/31913/2

Change in ...coreboot[master]: Fix 'unsigned int' to bare use of 'unsigned'

[build bot (Jenkins) (Code Review)]

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31913 )

Change subject: Fix 'unsigned int' to bare use of 'unsigned'
......................................................................

Patch Set 2:

(6 comments)

https://review.coreboot.org/#/c/31913/2/src/northbridge/amd/amdk8/reset_test... 
File src/northbridge/amd/amdk8/reset_test.c:

https://review.coreboot.org/#/c/31913/2/src/northbridge/amd/amdk8/reset_test... 
PS2, Line 64: static unsigned node_link_to_bus(unsigned int node, unsigned int link)
Prefer 'unsigned int' to bare use of 'unsigned'

https://review.coreboot.org/#/c/31913/2/src/northbridge/amd/pi/00630F01/nort... 
File src/northbridge/amd/pi/00630F01/northbridge.c:

https://review.coreboot.org/#/c/31913/2/src/northbridge/amd/pi/00630F01/nort... 
PS2, Line 171: static int reg_useable(unsigned reg, struct device *goal_dev, unsigned int goal_nodeid,
line over 80 characters

https://review.coreboot.org/#/c/31913/2/src/northbridge/amd/pi/00630F01/nort... 
PS2, Line 171: static int reg_useable(unsigned reg, struct device *goal_dev, unsigned int goal_nodeid,
Prefer 'unsigned int' to bare use of 'unsigned'

https://review.coreboot.org/#/c/31913/2/src/northbridge/amd/pi/00630F01/nort... 
PS2, Line 199: static struct resource *amdfam15_find_iopair(struct device *dev, unsigned int nodeid, unsigned int link)
line over 80 characters

https://review.coreboot.org/#/c/31913/2/src/northbridge/amd/pi/00730F01/nort... 
File src/northbridge/amd/pi/00730F01/northbridge.c:

https://review.coreboot.org/#/c/31913/2/src/northbridge/amd/pi/00730F01/nort... 
PS2, Line 172: static int reg_useable(unsigned int reg, struct device *goal_dev, unsigned int goal_nodeid,
line over 80 characters

https://review.coreboot.org/#/c/31913/2/src/northbridge/amd/pi/00730F01/nort... 
PS2, Line 200: static struct resource *amdfam16_find_iopair(struct device *dev, unsigned int nodeid, unsigned int link)
line over 80 characters

Change in ...coreboot[master]: Fix 'unsigned int' to bare use of 'unsigned'

[Subrata Banik (Code Review)]

Hello Kyösti Mälkki, Patrick Rudolph, Shelley Chen, Philipp Deppenwiese, build bot (Jenkins), Lijian Zhao, Furquan Shaikh,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/31913

to look at the new patch set (#3).

Change subject: Fix 'unsigned int' to bare use of 'unsigned'
......................................................................

Fix 'unsigned int' to bare use of 'unsigned'

Change-Id: Iee09b601045d7785a0977a4f7ed7385b1d311044
Signed-off-by: Subrata Banik 
---
M src/northbridge/amd/agesa/family12/northbridge.c
M src/northbridge/amd/agesa/family14/northbridge.c
M src/northbridge/amd/agesa/family15tn/northbridge.c
M src/northbridge/amd/agesa/family16kb/northbridge.c
M src/northbridge/amd/amdk8/reset_test.c
M src/northbridge/amd/pi/00630F01/northbridge.c
M src/northbridge/amd/pi/00660F01/northbridge.c
M src/northbridge/amd/pi/00730F01/northbridge.c
M src/northbridge/intel/sandybridge/gma.c
M src/northbridge/intel/sandybridge/raminit_common.c
M src/soc/intel/common/block/pcie/pcie.c
11 files changed, 127 insertions(+), 124 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/31913/3

Change in ...coreboot[master]: Fix 'unsigned int' to bare use of 'unsigned'

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31913 )

Change subject: Fix 'unsigned int' to bare use of 'unsigned'
......................................................................

Patch Set 3:
> The change is correct, but when you come across these please fix
> the entire tree with one bulk run. Eventually someone has to do
> that, it would be nice if not all of that was upto volunteering
> contributors.

[Subrata] I have address in new patch set.
> And for this particular set_subsystem(), maybe there is one
> standard case where one just writes these PCI config registers
> without any locking involved; that one should be promoted to
> globally available function and the dozens(?) of copies removed.

[Subrata] Let me check this as well.

Change in ...coreboot[master]: Fix 'unsigned int' to bare use of 'unsigned'

[Patrick Georgi (Code Review)]

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31913 )

Change subject: Fix 'unsigned int' to bare use of 'unsigned'
......................................................................

Patch Set 3: Code-Review+2

Change in ...coreboot[master]: Fix 'unsigned int' to bare use of 'unsigned'

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31913 )

Change subject: Fix 'unsigned int' to bare use of 'unsigned'
......................................................................

Patch Set 3: Code-Review+2

Change in ...coreboot[master]: Fix 'unsigned int' to bare use of 'unsigned'

[Subrata Banik (Code Review)]

Subrata Banik has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31913 )

Change subject: Fix 'unsigned int' to bare use of 'unsigned'
......................................................................

Fix 'unsigned int' to bare use of 'unsigned'

Change-Id: Iee09b601045d7785a0977a4f7ed7385b1d311044
Signed-off-by: Subrata Banik 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31913
Tested-by: build bot (Jenkins) 
Reviewed-by: Patrick Georgi 
Reviewed-by: Kyösti Mälkki 
---
M src/northbridge/amd/agesa/family12/northbridge.c
M src/northbridge/amd/agesa/family14/northbridge.c
M src/northbridge/amd/agesa/family15tn/northbridge.c
M src/northbridge/amd/agesa/family16kb/northbridge.c
M src/northbridge/amd/amdk8/reset_test.c
M src/northbridge/amd/pi/00630F01/northbridge.c
M src/northbridge/amd/pi/00660F01/northbridge.c
M src/northbridge/amd/pi/00730F01/northbridge.c
M src/northbridge/intel/sandybridge/gma.c
M src/northbridge/intel/sandybridge/raminit_common.c
M src/soc/intel/common/block/pcie/pcie.c
11 files changed, 127 insertions(+), 124 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Patrick Georgi: Looks good to me, approved
  Kyösti Mälkki: Looks good to me, approved

diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c
index c31cb70..290ab16 100644
--- a/src/northbridge/amd/agesa/family12/northbridge.c
+++ b/src/northbridge/amd/agesa/family12/northbridge.c
@@ -43,7 +43,7 @@
 static struct device *__f1_dev[FX_DEVS];
 static struct device *__f2_dev[FX_DEVS];
 static struct device *__f4_dev[FX_DEVS];
-static unsigned fx_devs = 0;
+static unsigned int fx_devs = 0;

struct dram_base_mask_t {
    u32 base; //[47:27] at [28:8]
@@ -129,7 +129,7 @@
    	die("Cannot find 0:0x18.[0|1]\n");
 }

-static u32 f1_read_config32(unsigned reg)
+static u32 f1_read_config32(unsigned int reg)
 {
    if (fx_devs == 0)
    	get_fx_devs();
@@ -137,7 +137,7 @@
    return pci_read_config32(__f1_dev[0], reg);
 }

-static void f1_write_config32(unsigned reg, u32 value)
+static void f1_write_config32(unsigned int reg, u32 value)
 {
    int i;
    if (fx_devs == 0)
@@ -176,11 +176,11 @@
 }

-static int reg_useable(unsigned reg, struct device *goal_dev,
-		       unsigned goal_nodeid, unsigned goal_link)
+static int reg_useable(unsigned int reg, struct device *goal_dev,
+		       unsigned int goal_nodeid, unsigned int goal_link)
 {
    struct resource *res;
-	unsigned nodeid, link = 0;
+	unsigned int nodeid, link = 0;
    int result;
    printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__);
    res = 0;
@@ -206,7 +206,7 @@
 }

static struct resource *amdfam12_find_iopair(struct device *dev,
-					     unsigned nodeid, unsigned link)
+					unsigned int nodeid, unsigned int link)
 {
    struct resource *resource;
    u32 result, reg;
@@ -324,7 +324,7 @@
 #if CONFIG_HW_MEM_HOLE_SIZEK != 0

struct hw_mem_hole_info {
-	unsigned hole_startk;
+	unsigned int hole_startk;
    int node_id;
 };

@@ -378,7 +378,7 @@
    		 u32 nodeid)
 {
    resource_t rbase, rend;
-	unsigned reg, link_num;
+	unsigned int reg, link_num;
    char buf[50];

printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__);
@@ -428,7 +428,7 @@
 extern struct device *vga_pri;    // the primary vga device, defined in device.c
 #endif

-static void create_vga_resource(struct device *dev, unsigned nodeid)
+static void create_vga_resource(struct device *dev, unsigned int nodeid)
 {
 struct bus *link;

@@ -461,7 +461,7 @@

static void set_resources(struct device *dev)
 {
-	unsigned nodeid;
+	unsigned int nodeid;
    struct bus *bus;
    struct resource *res;

@@ -488,7 +488,7 @@

static void domain_read_resources(struct device *dev)
 {
-	unsigned reg;
+	unsigned int reg;

printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__);

@@ -500,7 +500,7 @@
    	limit = f1_read_config32(reg + 0x04);
    	/* Is this register allocated? */
    	if ((base & 3) != 0) {
-			unsigned nodeid, reg_link;
+			unsigned int nodeid, reg_link;
    		struct device *reg_dev;
    		if (reg < 0xc0) { // mmio
    			nodeid = (limit & 0xf) + (base&0x30);
@@ -622,7 +622,7 @@
    	/* split the region to accommodate pci memory space */
    	if ((basek < 4*1024*1024) && (limitk > mmio_basek)) {
    		if (basek <= mmio_basek) {
-				unsigned pre_sizek;
+				unsigned int pre_sizek;
    			pre_sizek = mmio_basek - basek;
    			if (pre_sizek > 0) {
    				ram_resource(dev, idx, basek, pre_sizek);
diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c
index 381d198..a52f7ec 100644
--- a/src/northbridge/amd/agesa/family14/northbridge.c
+++ b/src/northbridge/amd/agesa/family14/northbridge.c
@@ -40,7 +40,7 @@
 static struct device *__f1_dev[FX_DEVS];
 static struct device *__f2_dev[FX_DEVS];
 static struct device *__f4_dev[FX_DEVS];
-static unsigned fx_devs = 0;
+static unsigned int fx_devs = 0;

struct dram_base_mask_t {
@@ -127,14 +127,14 @@
    }
 }

-static u32 f1_read_config32(unsigned reg)
+static u32 f1_read_config32(unsigned int reg)
 {
    if (fx_devs == 0)
    	get_fx_devs();
    return pci_read_config32(__f1_dev[0], reg);
 }

-static void f1_write_config32(unsigned reg, u32 value)
+static void f1_write_config32(unsigned int reg, u32 value)
 {
    int i;
    if (fx_devs == 0)
@@ -169,11 +169,11 @@

}

-static int reg_useable(unsigned reg, struct device *goal_dev,
-		       unsigned goal_nodeid, unsigned goal_link)
+static int reg_useable(unsigned int reg, struct device *goal_dev,
+		       unsigned int goal_nodeid, unsigned int goal_link)
 {
    struct resource *res;
-	unsigned nodeid, link = 0;
+	unsigned int nodeid, link = 0;
    int result;
    res = 0;
    for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) {
@@ -197,7 +197,7 @@
 }

static struct resource *amdfam14_find_iopair(struct device *dev,
-					     unsigned nodeid, unsigned link)
+			unsigned int nodeid, unsigned int link)
 {
    struct resource *resource;
    u32 result, reg;
@@ -314,7 +314,7 @@
 #if CONFIG_HW_MEM_HOLE_SIZEK != 0

struct hw_mem_hole_info {
-	unsigned hole_startk;
+	unsigned int hole_startk;
    int node_id;
 };

@@ -365,7 +365,7 @@
    		 u32 nodeid)
 {
    resource_t rbase, rend;
-	unsigned reg, link_num;
+	unsigned int reg, link_num;
    char buf[50];

printk(BIOS_DEBUG, "\nFam14h - %s\n", __func__);
@@ -414,7 +414,7 @@
 extern struct device *vga_pri;	// the primary vga device, defined in device.c
 #endif

-static void create_vga_resource(struct device *dev, unsigned nodeid)
+static void create_vga_resource(struct device *dev, unsigned int nodeid)
 {
    struct bus *link;

@@ -448,7 +448,7 @@

static void nb_set_resources(struct device *dev)
 {
-	unsigned nodeid;
+	unsigned int nodeid;
    struct bus *bus;
    struct resource *res;

@@ -475,7 +475,7 @@

static void domain_read_resources(struct device *dev)
 {
-	unsigned reg;
+	unsigned int reg;

printk(BIOS_DEBUG, "\nFam14h - %s\n", __func__);

@@ -487,7 +487,7 @@
    	limit = f1_read_config32(reg + 0x04);
    	/* Is this register allocated? */
    	if ((base & 3) != 0) {
-			unsigned nodeid, reg_link;
+			unsigned int nodeid, reg_link;
    		struct device *reg_dev;
    		if (reg < 0xc0) {	// mmio
    			nodeid = (limit & 0xf) + (base & 0x30);
@@ -600,7 +600,7 @@
    	/* split the region to accommodate pci memory space */
    	if ((basek < 4 * 1024 * 1024) && (limitk > mmio_basek)) {
    		if (basek <= mmio_basek) {
-				unsigned pre_sizek;
+				unsigned int pre_sizek;
    			pre_sizek = mmio_basek - basek;
    			if (pre_sizek > 0) {
    				ram_resource(dev, idx, basek,
diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c
index 367feca..d73ad72 100644
--- a/src/northbridge/amd/agesa/family15tn/northbridge.c
+++ b/src/northbridge/amd/agesa/family15tn/northbridge.c
@@ -45,13 +45,13 @@
    u32 mask; //[47:27] at [28:8] and enable at bit 0
 } dram_base_mask_t;

-static unsigned node_nums;
-static unsigned sblink;
+static unsigned int node_nums;
+static unsigned int sblink;
 static struct device *__f0_dev[MAX_NODE_NUMS];
 static struct device *__f1_dev[MAX_NODE_NUMS];
 static struct device *__f2_dev[MAX_NODE_NUMS];
 static struct device *__f4_dev[MAX_NODE_NUMS];
-static unsigned fx_devs = 0;
+static unsigned int fx_devs = 0;

static dram_base_mask_t get_dram_base_mask(u32 nodeid)
 {
@@ -120,14 +120,14 @@
    printk(BIOS_DEBUG, "fx_devs=0x%x\n", fx_devs);
 }

-static u32 f1_read_config32(unsigned reg)
+static u32 f1_read_config32(unsigned int reg)
 {
    if (fx_devs == 0)
    	get_fx_devs();
    return pci_read_config32(__f1_dev[0], reg);
 }

-static void f1_write_config32(unsigned reg, u32 value)
+static void f1_write_config32(unsigned int reg, u32 value)
 {
    int i;
    if (fx_devs == 0)
@@ -165,11 +165,11 @@
  *  @retval 0  resource exists, not usable
  *  @retval 1  resource exist, resource has been allocated before
  */
-static int reg_useable(unsigned reg, struct device *goal_dev, unsigned goal_nodeid,
-			unsigned goal_link)
+static int reg_useable(unsigned int reg, struct device *goal_dev,
+			unsigned int goal_nodeid, unsigned int goal_link)
 {
    struct resource *res;
-	unsigned nodeid, link = 0;
+	unsigned int nodeid, link = 0;
    int result;
    res = 0;
    for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) {
@@ -193,7 +193,8 @@
    return result;
 }

-static struct resource *amdfam15_find_iopair(struct device *dev, unsigned nodeid, unsigned link)
+static struct resource *amdfam15_find_iopair(struct device *dev,
+		unsigned int nodeid, unsigned int link)
 {
    struct resource *resource;
    u32 free_reg, reg;
@@ -311,7 +312,7 @@
 static void set_resource(struct device *dev, struct resource *resource, u32 nodeid)
 {
    resource_t rbase, rend;
-	unsigned reg, link_num;
+	unsigned int reg, link_num;
    char buf[50];

/* Make certain the resource has actually been set */
@@ -359,7 +360,7 @@
  * but it is too difficult to deal with the resource allocation magic.
  */

-static void create_vga_resource(struct device *dev, unsigned nodeid)
+static void create_vga_resource(struct device *dev, unsigned int nodeid)
 {
    struct bus *link;

@@ -389,7 +390,7 @@

static void nb_set_resources(struct device *dev)
 {
-	unsigned nodeid;
+	unsigned int nodeid;
    struct bus *bus;
    struct resource *res;

@@ -572,7 +573,7 @@

static void domain_read_resources(struct device *dev)
 {
-	unsigned reg;
+	unsigned int reg;

/* Find the already assigned resource pairs */
    get_fx_devs();
@@ -582,7 +583,7 @@
    	limit = f1_read_config32(reg + 0x04);
    	/* Is this register allocated? */
    	if ((base & 3) != 0) {
-			unsigned nodeid, reg_link;
+			unsigned int nodeid, reg_link;
    		struct device *reg_dev;
    		if (reg < 0xc0) { // mmio
    			nodeid = (limit & 0xf) + (base&0x30);
@@ -609,7 +610,7 @@

#if CONFIG_HW_MEM_HOLE_SIZEK != 0
 struct hw_mem_hole_info {
-	unsigned hole_startk;
+	unsigned int hole_startk;
    int node_id;
 };
 static struct hw_mem_hole_info get_hw_mem_hole_info(void)
@@ -724,7 +725,7 @@
    	/* split the region to accommodate pci memory space */
    	if ((basek < 4*1024*1024) && (limitk > mmio_basek)) {
    		if (basek <= mmio_basek) {
-				unsigned pre_sizek;
+				unsigned int pre_sizek;
    			pre_sizek = mmio_basek - basek;
    			if (pre_sizek > 0) {
    				ram_resource(dev, (idx | i), basek, pre_sizek);
@@ -771,7 +772,7 @@
    node_nums = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; //NodeCnt[2:0]
 }

-static void add_more_links(struct device *dev, unsigned total_links)
+static void add_more_links(struct device *dev, unsigned int total_links)
 {
    struct bus *link, *last = NULL;
    int link_num;
@@ -814,8 +815,8 @@
    int i,j;
    int coreid_bits;
    int core_max = 0;
-	unsigned ApicIdCoreIdSize;
-	unsigned core_nums;
+	unsigned int ApicIdCoreIdSize;
+	unsigned int core_nums;
    int siblings = 0;
    unsigned int family;

@@ -841,7 +842,7 @@
    cpu_bus = dev->link_list;
    for (i = 0; i < node_nums; i++) {
    	struct device *cdb_dev;
-		unsigned devn;
+		unsigned int devn;
    	struct bus *pbus;

devn = DEV_CDB + i;
diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c
index 44f49ea..7ca5a6e 100644
--- a/src/northbridge/amd/agesa/family16kb/northbridge.c
+++ b/src/northbridge/amd/agesa/family16kb/northbridge.c
@@ -44,13 +44,13 @@
    u32 mask; //[47:27] at [28:8] and enable at bit 0
 } dram_base_mask_t;

-static unsigned node_nums;
-static unsigned sblink;
+static unsigned int node_nums;
+static unsigned int sblink;
 static struct device *__f0_dev[MAX_NODE_NUMS];
 static struct device *__f1_dev[MAX_NODE_NUMS];
 static struct device *__f2_dev[MAX_NODE_NUMS];
 static struct device *__f4_dev[MAX_NODE_NUMS];
-static unsigned fx_devs = 0;
+static unsigned int fx_devs = 0;

static dram_base_mask_t get_dram_base_mask(u32 nodeid)
 {
@@ -119,14 +119,14 @@
    printk(BIOS_DEBUG, "fx_devs=0x%x\n", fx_devs);
 }

-static u32 f1_read_config32(unsigned reg)
+static u32 f1_read_config32(unsigned int reg)
 {
    if (fx_devs == 0)
    	get_fx_devs();
    return pci_read_config32(__f1_dev[0], reg);
 }

-static void f1_write_config32(unsigned reg, u32 value)
+static void f1_write_config32(unsigned int reg, u32 value)
 {
    int i;
    if (fx_devs == 0)
@@ -164,11 +164,11 @@
  *  @retval 0  resource exists, not usable
  *  @retval 1  resource exist, resource has been allocated before
  */
-static int reg_useable(unsigned reg, struct device *goal_dev, unsigned goal_nodeid,
-			unsigned goal_link)
+static int reg_useable(unsigned int reg, struct device *goal_dev,
+			unsigned int goal_nodeid, unsigned int goal_link)
 {
    struct resource *res;
-	unsigned nodeid, link = 0;
+	unsigned int nodeid, link = 0;
    int result;
    res = 0;
    for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) {
@@ -192,7 +192,8 @@
    return result;
 }

-static struct resource *amdfam16_find_iopair(struct device *dev, unsigned nodeid, unsigned link)
+static struct resource *amdfam16_find_iopair(struct device *dev,
+			unsigned int nodeid, unsigned int link)
 {
    struct resource *resource;
    u32 free_reg, reg;
@@ -310,7 +311,7 @@
 static void set_resource(struct device *dev, struct resource *resource, u32 nodeid)
 {
    resource_t rbase, rend;
-	unsigned reg, link_num;
+	unsigned int reg, link_num;
    char buf[50];

/* Make certain the resource has actually been set */
@@ -358,7 +359,7 @@
  * but it is too difficult to deal with the resource allocation magic.
  */

-static void create_vga_resource(struct device *dev, unsigned nodeid)
+static void create_vga_resource(struct device *dev, unsigned int nodeid)
 {
    struct bus *link;

@@ -388,7 +389,7 @@

static void set_resources(struct device *dev)
 {
-	unsigned nodeid;
+	unsigned int nodeid;
    struct bus *bus;
    struct resource *res;

@@ -409,7 +410,6 @@
    }
 }

-
 static unsigned long acpi_fill_hest(acpi_hest_t *hest)
 {
    void *addr, *current;
@@ -589,7 +589,7 @@

static void domain_read_resources(struct device *dev)
 {
-	unsigned reg;
+	unsigned int reg;

/* Find the already assigned resource pairs */
    get_fx_devs();
@@ -599,7 +599,7 @@
    	limit = f1_read_config32(reg + 0x04);
    	/* Is this register allocated? */
    	if ((base & 3) != 0) {
-			unsigned nodeid, reg_link;
+			unsigned int nodeid, reg_link;
    		struct device *reg_dev;
    		if (reg < 0xc0) { // mmio
    			nodeid = (limit & 0xf) + (base&0x30);
@@ -626,7 +626,7 @@

#if CONFIG_HW_MEM_HOLE_SIZEK != 0
 struct hw_mem_hole_info {
-	unsigned hole_startk;
+	unsigned int hole_startk;
    int node_id;
 };
 static struct hw_mem_hole_info get_hw_mem_hole_info(void)
@@ -742,7 +742,7 @@
    	/* split the region to accommodate pci memory space */
    	if ((basek < 4*1024*1024) && (limitk > mmio_basek)) {
    		if (basek <= mmio_basek) {
-				unsigned pre_sizek;
+				unsigned int pre_sizek;
    			pre_sizek = mmio_basek - basek;
    			if (pre_sizek > 0) {
    				ram_resource(dev, (idx | i), basek, pre_sizek);
@@ -798,7 +798,7 @@
    node_nums = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; //NodeCnt[2:0]
 }

-static void add_more_links(struct device *dev, unsigned total_links)
+static void add_more_links(struct device *dev, unsigned int total_links)
 {
    struct bus *link, *last = NULL;
    int link_num;
@@ -841,8 +841,8 @@
    int i,j;
    int coreid_bits;
    int core_max = 0;
-	unsigned ApicIdCoreIdSize;
-	unsigned core_nums;
+	unsigned int ApicIdCoreIdSize;
+	unsigned int core_nums;
    int siblings = 0;
    unsigned int family;

@@ -868,7 +868,7 @@
    cpu_bus = dev->link_list;
    for (i = 0; i < node_nums; i++) {
    	struct device *cdb_dev;
-		unsigned devn;
+		unsigned int devn;
    	struct bus *pbus;

devn = DEV_CDB + i;
diff --git a/src/northbridge/amd/amdk8/reset_test.c b/src/northbridge/amd/amdk8/reset_test.c
index c711ac1..214aed4 100644
--- a/src/northbridge/amd/amdk8/reset_test.c
+++ b/src/northbridge/amd/amdk8/reset_test.c
@@ -16,7 +16,7 @@
 #include <cpu/x86/lapic.h>
 #include "amdk8.h"

-static inline int cpu_init_detected(unsigned nodeid)
+static inline int cpu_init_detected(unsigned int nodeid)
 {
    u32 htic;
    pci_devfn_t dev;
@@ -61,7 +61,7 @@
    pci_io_write_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL, htic);
 }

-static unsigned node_link_to_bus(unsigned node, unsigned link)
+static unsigned int node_link_to_bus(unsigned int node, unsigned int link)
 {
    u8 reg;

@@ -88,7 +88,7 @@
    return ((reg>>8) & 3);
 }

-unsigned int get_sbbusn(unsigned sblk)
+unsigned int get_sbbusn(unsigned int sblk)
 {
    return node_link_to_bus(0, sblk);
 }
diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c
index 3f86427..2b94daa 100644
--- a/src/northbridge/amd/pi/00630F01/northbridge.c
+++ b/src/northbridge/amd/pi/00630F01/northbridge.c
@@ -48,13 +48,13 @@
    u32 mask; //[47:27] at [28:8] and enable at bit 0
 } dram_base_mask_t;

-static unsigned node_nums;
-static unsigned sblink;
+static unsigned int node_nums;
+static unsigned int sblink;
 static struct device *__f0_dev[MAX_NODE_NUMS];
 static struct device *__f1_dev[MAX_NODE_NUMS];
 static struct device *__f2_dev[MAX_NODE_NUMS];
 static struct device *__f4_dev[MAX_NODE_NUMS];
-static unsigned fx_devs = 0;
+static unsigned int fx_devs = 0;

static dram_base_mask_t get_dram_base_mask(u32 nodeid)
 {
@@ -123,14 +123,14 @@
    printk(BIOS_DEBUG, "fx_devs = 0x%x\n", fx_devs);
 }

-static u32 f1_read_config32(unsigned reg)
+static u32 f1_read_config32(unsigned int reg)
 {
    if (fx_devs == 0)
    	get_fx_devs();
    return pci_read_config32(__f1_dev[0], reg);
 }

-static void f1_write_config32(unsigned reg, u32 value)
+static void f1_write_config32(unsigned int reg, u32 value)
 {
    int i;
    if (fx_devs == 0)
@@ -168,11 +168,11 @@
  *  @retval 0  resource exists, but is not usable
  *  @retval 1  resource exists, but has been allocated before
  */
-static int reg_useable(unsigned reg, struct device *goal_dev, unsigned goal_nodeid,
-			unsigned goal_link)
+static int reg_useable(unsigned int reg, struct device *goal_dev,
+		unsigned int goal_nodeid, unsigned int goal_link)
 {
    struct resource *res;
-	unsigned nodeid, link = 0;
+	unsigned int nodeid, link = 0;
    int result;
    res = 0;
    for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) {
@@ -196,7 +196,8 @@
    return result;
 }

-static struct resource *amdfam15_find_iopair(struct device *dev, unsigned nodeid, unsigned link)
+static struct resource *amdfam15_find_iopair(struct device *dev,
+		unsigned int nodeid, unsigned int link)
 {
    struct resource *resource;
    u32 free_reg, reg;
@@ -362,7 +363,7 @@
  * but it is too difficult to deal with the resource allocation magic.
  */

-static void create_vga_resource(struct device *dev, unsigned nodeid)
+static void create_vga_resource(struct device *dev, unsigned int nodeid)
 {
    struct bus *link;

@@ -394,7 +395,7 @@

static void set_resources(struct device *dev)
 {
-	unsigned nodeid;
+	unsigned int nodeid;
    struct bus *bus;
    struct resource *res;

@@ -573,7 +574,7 @@

static void domain_read_resources(struct device *dev)
 {
-	unsigned reg;
+	unsigned int reg;

/* Find the already assigned resource pairs */
    get_fx_devs();
@@ -583,7 +584,7 @@
    	limit = f1_read_config32(reg + 0x04);
    	/* Is this register allocated? */
    	if ((base & 3) != 0) {
-			unsigned nodeid, reg_link;
+			unsigned int nodeid, reg_link;
    		struct device *reg_dev;
    		if (reg < 0xc0) { // mmio
    			nodeid = (limit & 0xf) + (base&0x30);
@@ -625,7 +626,7 @@

#if CONFIG_HW_MEM_HOLE_SIZEK != 0
 struct hw_mem_hole_info {
-	unsigned hole_startk;
+	unsigned int hole_startk;
    int node_id;
 };
 static struct hw_mem_hole_info get_hw_mem_hole_info(void)
@@ -742,7 +743,7 @@
    	/* split the region to accommodate pci memory space */
    	if ((basek < 4*1024*1024) && (limitk > mmio_basek)) {
    		if (basek <= mmio_basek) {
-				unsigned pre_sizek;
+				unsigned int pre_sizek;
    			pre_sizek = mmio_basek - basek;
    			if (pre_sizek > 0) {
    				ram_resource(dev, (idx | i), basek, pre_sizek);
@@ -833,8 +834,8 @@
    int i,j;
    int coreid_bits;
    int core_max = 0;
-	unsigned ApicIdCoreIdSize;
-	unsigned core_nums;
+	unsigned int ApicIdCoreIdSize;
+	unsigned int core_nums;
    int siblings = 0;
    unsigned int family;
    u32 modules = 0;
@@ -876,7 +877,7 @@
    cpu_bus = dev->link_list;
    for (i = 0; i < node_nums; i++) {
    	struct device *cdb_dev;
-		unsigned devn;
+		unsigned int devn;
    	struct bus *pbus;

devn = DEV_CDB + i;
diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c
index bf7c59a..43df725 100644
--- a/src/northbridge/amd/pi/00660F01/northbridge.c
+++ b/src/northbridge/amd/pi/00660F01/northbridge.c
@@ -573,7 +573,7 @@

static void domain_read_resources(struct device *dev)
 {
-	unsigned reg;
+	unsigned int reg;

/* Find the already assigned resource pairs */
    get_fx_devs();
@@ -583,7 +583,7 @@
    	limit = f1_read_config32(reg + 0x04);
    	/* Is this register allocated? */
    	if ((base & 3) != 0) {
-			unsigned nodeid, reg_link;
+			unsigned int nodeid, reg_link;
    		struct device *reg_dev;
    		if (reg < 0xc0) { // mmio
    			nodeid = (limit & 0xf) + (base & 0x30);
@@ -621,7 +621,7 @@

#if CONFIG_HW_MEM_HOLE_SIZEK != 0
 struct hw_mem_hole_info {
-	unsigned hole_startk;
+	unsigned int hole_startk;
    int node_id;
 };
 static struct hw_mem_hole_info get_hw_mem_hole_info(void)
@@ -738,7 +738,7 @@
    	/* split the region to accommodate pci memory space */
    	if ((basek < 4*1024*1024) && (limitk > mmio_basek)) {
    		if (basek <= mmio_basek) {
-				unsigned pre_sizek;
+				unsigned int pre_sizek;
    			pre_sizek = mmio_basek - basek;
    			if (pre_sizek > 0) {
    				ram_resource(dev, (idx | i), basek, pre_sizek);
diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c
index eb38c42..926208c 100644
--- a/src/northbridge/amd/pi/00730F01/northbridge.c
+++ b/src/northbridge/amd/pi/00730F01/northbridge.c
@@ -49,13 +49,13 @@
    u32 mask; //[47:27] at [28:8] and enable at bit 0
 } dram_base_mask_t;

-static unsigned node_nums;
-static unsigned sblink;
+static unsigned int node_nums;
+static unsigned int sblink;
 static struct device *__f0_dev[MAX_NODE_NUMS];
 static struct device *__f1_dev[MAX_NODE_NUMS];
 static struct device *__f2_dev[MAX_NODE_NUMS];
 static struct device *__f4_dev[MAX_NODE_NUMS];
-static unsigned fx_devs = 0;
+static unsigned int fx_devs = 0;

static dram_base_mask_t get_dram_base_mask(u32 nodeid)
 {
@@ -124,14 +124,14 @@
    printk(BIOS_DEBUG, "fx_devs = 0x%x\n", fx_devs);
 }

-static u32 f1_read_config32(unsigned reg)
+static u32 f1_read_config32(unsigned int reg)
 {
    if (fx_devs == 0)
    	get_fx_devs();
    return pci_read_config32(__f1_dev[0], reg);
 }

-static void f1_write_config32(unsigned reg, u32 value)
+static void f1_write_config32(unsigned int reg, u32 value)
 {
    int i;
    if (fx_devs == 0)
@@ -169,11 +169,11 @@
  *  @retval 0  resource exists, not usable
  *  @retval 1  resource exist, resource has been allocated before
  */
-static int reg_useable(unsigned reg, struct device *goal_dev, unsigned goal_nodeid,
-			unsigned goal_link)
+static int reg_useable(unsigned int reg, struct device *goal_dev,
+		unsigned int goal_nodeid, unsigned int goal_link)
 {
    struct resource *res;
-	unsigned nodeid, link = 0;
+	unsigned int nodeid, link = 0;
    int result;
    res = 0;
    for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) {
@@ -197,7 +197,8 @@
    return result;
 }

-static struct resource *amdfam16_find_iopair(struct device *dev, unsigned nodeid, unsigned link)
+static struct resource *amdfam16_find_iopair(struct device *dev,
+		unsigned int nodeid, unsigned int link)
 {
    struct resource *resource;
    u32 free_reg, reg;
@@ -315,7 +316,7 @@
 static void set_resource(struct device *dev, struct resource *resource, u32 nodeid)
 {
    resource_t rbase, rend;
-	unsigned reg, link_num;
+	unsigned int reg, link_num;
    char buf[50];

/* Make certain the resource has actually been set */
@@ -363,7 +364,7 @@
  * but it is too difficult to deal with the resource allocation magic.
  */

-static void create_vga_resource(struct device *dev, unsigned nodeid)
+static void create_vga_resource(struct device *dev, unsigned int nodeid)
 {
    struct bus *link;

@@ -393,7 +394,7 @@

static void set_resources(struct device *dev)
 {
-	unsigned nodeid;
+	unsigned int nodeid;
    struct bus *bus;
    struct resource *res;

@@ -807,7 +808,7 @@

static void domain_read_resources(struct device *dev)
 {
-	unsigned reg;
+	unsigned int reg;

/* Find the already assigned resource pairs */
    get_fx_devs();
@@ -817,7 +818,7 @@
    	limit = f1_read_config32(reg + 0x04);
    	/* Is this register allocated? */
    	if ((base & 3) != 0) {
-			unsigned nodeid, reg_link;
+			unsigned int nodeid, reg_link;
    		struct device *reg_dev;
    		if (reg < 0xc0) { // mmio
    			nodeid = (limit & 0xf) + (base&0x30);
@@ -854,7 +855,7 @@

#if CONFIG_HW_MEM_HOLE_SIZEK != 0
 struct hw_mem_hole_info {
-	unsigned hole_startk;
+	unsigned int hole_startk;
    int node_id;
 };
 static struct hw_mem_hole_info get_hw_mem_hole_info(void)
@@ -971,7 +972,7 @@
    	/* split the region to accommodate pci memory space */
    	if ((basek < 4*1024*1024) && (limitk > mmio_basek)) {
    		if (basek <= mmio_basek) {
-				unsigned pre_sizek;
+				unsigned int pre_sizek;
    			pre_sizek = mmio_basek - basek;
    			if (pre_sizek > 0) {
    				ram_resource(dev, (idx | i), basek, pre_sizek);
@@ -1028,7 +1029,7 @@
    node_nums = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; //NodeCnt[2:0]
 }

-static void add_more_links(struct device *dev, unsigned total_links)
+static void add_more_links(struct device *dev, unsigned int total_links)
 {
    struct bus *link, *last = NULL;
    int link_num;
@@ -1071,8 +1072,8 @@
    int i,j;
    int coreid_bits;
    int core_max = 0;
-	unsigned ApicIdCoreIdSize;
-	unsigned core_nums;
+	unsigned int ApicIdCoreIdSize;
+	unsigned int core_nums;
    int siblings = 0;
    unsigned int family;
    u32 modules = 0;
@@ -1114,7 +1115,7 @@
    cpu_bus = dev->link_list;
    for (i = 0; i < node_nums; i++) {
    	struct device *cdb_dev;
-		unsigned devn;
+		unsigned int devn;
    	struct bus *pbus;

devn = DEV_CDB + i;
diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c
index 00180fe..d302c52 100644
--- a/src/northbridge/intel/sandybridge/gma.c
+++ b/src/northbridge/intel/sandybridge/gma.c
@@ -300,7 +300,7 @@
 #define GTT_RETRY 1000
 int gtt_poll(u32 reg, u32 mask, u32 value)
 {
-	unsigned try = GTT_RETRY;
+	unsigned int try = GTT_RETRY;
    u32 data;

while (try--) {
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c
index fda662f..55df03b 100644
--- a/src/northbridge/intel/sandybridge/raminit_common.c
+++ b/src/northbridge/intel/sandybridge/raminit_common.c
@@ -1577,8 +1577,8 @@

static void fill_pattern0(ramctr_timing * ctrl, int channel, u32 a, u32 b)
 {
-	unsigned j;
-	unsigned channel_offset =
+	unsigned int j;
+	unsigned int channel_offset =
        get_precedening_channels(ctrl, channel) * 0x40;
    for (j = 0; j < 16; j++)
    	write32((void *)(0x04000000 + channel_offset + 4 * j), j & 2 ? b : a);
@@ -1595,10 +1595,10 @@

static void fill_pattern1(ramctr_timing * ctrl, int channel)
 {
-	unsigned j;
-	unsigned channel_offset =
+	unsigned int j;
+	unsigned int channel_offset =
        get_precedening_channels(ctrl, channel) * 0x40;
-	unsigned channel_step = 0x40 * num_of_channels(ctrl);
+	unsigned int channel_step = 0x40 * num_of_channels(ctrl);
    for (j = 0; j < 16; j++)
    	write32((void *)(0x04000000 + channel_offset + j * 4), 0xffffffff);
    for (j = 0; j < 16; j++)
@@ -2125,10 +2125,10 @@

static void fill_pattern5(ramctr_timing * ctrl, int channel, int patno)
 {
-	unsigned i, j;
-	unsigned channel_offset =
+	unsigned int i, j;
+	unsigned int channel_offset =
        get_precedening_channels(ctrl, channel) * 0x40;
-	unsigned channel_step = 0x40 * num_of_channels(ctrl);
+	unsigned int channel_step = 0x40 * num_of_channels(ctrl);

if (patno) {
    	u8 base8 = 0x80 >> ((patno - 1) % 8);
diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c
index 0a5e1bf..8295765 100644
--- a/src/soc/intel/common/block/pcie/pcie.c
+++ b/src/soc/intel/common/block/pcie/pcie.c
@@ -73,7 +73,7 @@
 }

static void pcie_dev_set_subsystem(struct device *dev,
-		unsigned vendor, unsigned device)
+		unsigned int vendor, unsigned int device)
 {
    pci_write_config32(dev, PCIE_SUBSYSTEM_VENDOR_ID,
    		((device & 0xffff) << 16) | (vendor & 0xffff));