Maximilian Brune has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80746?usp=email )
Change subject: mb/emulation/qemu-riscv: Change to -bios option ......................................................................
mb/emulation/qemu-riscv: Change to -bios option
This changes the virt target so that it can be run with the -bios option and a pflash backend for the flash. QEMU can now be run as follows:
qemu -M virt -m 1G -nographic -bios build/coreboot.rom \ -drive if=pflash,file=./build/coreboot.rom,format=raw
coreboot will start in DRAM, but still have a flash to put CBFS onto and to load subsequent stages and payload from. Probing ram size on riscv is currently not working therefore the RAM size stays fixed for now.
Signed-off-by: Maximilian Brune maximilian.brune@9elements.com Change-Id: I009d97fa3e13068b91c604e987e50a65e525407d --- M Documentation/mainboard/emulation/qemu-riscv.md M Makefile.mk M src/Kconfig M src/mainboard/emulation/qemu-riscv/Kconfig M src/mainboard/emulation/qemu-riscv/Makefile.mk A src/mainboard/emulation/qemu-riscv/cbmem.c A src/mainboard/emulation/qemu-riscv/chip.c M src/mainboard/emulation/qemu-riscv/devicetree.cb M src/mainboard/emulation/qemu-riscv/include/mainboard/addressmap.h M src/mainboard/emulation/qemu-riscv/mainboard.c M src/mainboard/emulation/qemu-riscv/memlayout.ld M src/mainboard/emulation/qemu-riscv/rom_media.c M src/mainboard/emulation/qemu-riscv/romstage.c M src/soc/ucb/riscv/cbmem.c 14 files changed, 138 insertions(+), 57 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/80746/1
diff --git a/Documentation/mainboard/emulation/qemu-riscv.md b/Documentation/mainboard/emulation/qemu-riscv.md index ed2c6d5..9ccc1b7 100644 --- a/Documentation/mainboard/emulation/qemu-riscv.md +++ b/Documentation/mainboard/emulation/qemu-riscv.md @@ -3,6 +3,9 @@ ## Building coreboot and running it in QEMU
- Configure coreboot and run `make` as usual -- Run `util/riscv/make-spike-elf.sh build/coreboot.rom build/coreboot.elf` to - convert coreboot to an ELF that QEMU can load -- Run `qemu-system-riscv64 -M virt -m 1024M -nographic -kernel build/coreboot.elf` + +Run QEMU +``` +qemu-system-riscv64 -M virt -m 1G -nographic -bios build/coreboot.rom \ + -drive if=pflash,file=./build/coreboot.rom,format=raw +``` diff --git a/Makefile.mk b/Makefile.mk index f7b98c7..3f93749 100644 --- a/Makefile.mk +++ b/Makefile.mk @@ -492,7 +492,7 @@
CFLAGS_common += -pipe -g -nostdinc -std=gnu11 CFLAGS_common += -nostdlib -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes -CFLAGS_common += -Wwrite-strings -Wredundant-decls -Wno-trigraphs -Wimplicit-fallthrough +CFLAGS_common += -Wwrite-strings -Wredundant-decls -Wno-trigraphs -Wimplicit-fallthrough -Wno-unused-function CFLAGS_common += -Wshadow -Wdate-time -Wtype-limits -Wvla -Wold-style-definition CFLAGS_common += -Wdangling-else -Wmissing-include-dirs CFLAGS_common += -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer @@ -1387,7 +1387,8 @@ rend=$$(($$y)) ; \ if [ $$pstart -lt $$rend -a $$rstart -lt $$pend ]; then \ echo "ERROR: Ramstage region _$$rname overlapped by:" \ - $(check-ramstage-overlap-files) ; \ + "$$pstart $$pend $$rstart $$rend" \ + " $$x " ; \ exit 1 ; \ fi ; \ rname= ; rstart= ; rend= ; \ diff --git a/src/Kconfig b/src/Kconfig index 2bcc3ce..1ba90a8 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -245,7 +245,7 @@
config SEPARATE_ROMSTAGE bool "Build a separate romstage" - default y + default n #TODO change back after rebase help Build a separate romstage that is loaded by bootblock. With this option disabled the romstage sources are linked inside the bootblock diff --git a/src/mainboard/emulation/qemu-riscv/Kconfig b/src/mainboard/emulation/qemu-riscv/Kconfig index 091c432..538355c 100644 --- a/src/mainboard/emulation/qemu-riscv/Kconfig +++ b/src/mainboard/emulation/qemu-riscv/Kconfig @@ -23,12 +23,19 @@
config BOARD_SPECIFIC_OPTIONS def_bool y - select SOC_UCB_RISCV - select BOARD_ROMSIZE_KB_16384 + select BOARD_ROMSIZE_KB_32768 select BOOT_DEVICE_NOT_SPI_FLASH select MISSING_BOARD_RESET select DRIVERS_UART_8250MEM select RISCV_HAS_OPENSBI + select ARCH_RISCV_S + select ARCH_RISCV_U + select ARCH_RISCV_PMP + select ARCH_BOOTBLOCK_RISCV + select ARCH_VERSTAGE_RISCV + select ARCH_ROMSTAGE_RISCV + select ARCH_RAMSTAGE_RISCV + select RISCV_USE_ARCH_TIMER
config MEMLAYOUT_LD_FILE string @@ -44,28 +51,66 @@ int default 1
+config RISCV_ARCH + string + default "rv64imafd" + +config RISCV_ABI + string + default "lp64d" + +config RISCV_CODEMODEL + string + default "medany" + +config RISCV_WORKING_HARTID + int + default 0 + +choice + prompt "DRAM SIZE MB" + help + Select the size of the DDR qemu will provide. + Note: You MUST specify the same memory size on the qemu cmdline. + + config COREBOOT_DDR_SIZE_256M + bool "256 MB" + help + Choose this option if you want coreboot to find 256MB DDR. + + config COREBOOT_DDR_SIZE_512M + bool "512 MB" + help + Choose this option if you want coreboot to find 512MB DDR. + + config COREBOOT_DDR_SIZE_1024M + bool "1024 MB" + help + Choose this option if you want coreboot to find 1024MB DDR. + + config COREBOOT_DDR_SIZE_2048M + bool "2048 MB" + help + Choose this option if you want coreboot to find 2048MB DDR. +endchoice + config DRAM_SIZE_MB int - default 32768 + default 1024 + default 256 if COREBOOT_DDR_SIZE_256M + default 512 if COREBOOT_DDR_SIZE_512M + default 1024 if COREBOOT_DDR_SIZE_1024M + default 2048 if COREBOOT_DDR_SIZE_2048M + +#config SEPARATE_ROMSTAGE +# default n
config OPENSBI_PLATFORM string default "generic"
-# ugly, but CBFS is placed in DRAM... config OPENSBI_TEXT_START hex - default 0x80040000 if COREBOOT_ROMSIZE_KB_256 - default 0x80080000 if COREBOOT_ROMSIZE_KB_512 - default 0x80100000 if COREBOOT_ROMSIZE_KB_1024 - default 0x80200000 if COREBOOT_ROMSIZE_KB_2048 - default 0x80400000 if COREBOOT_ROMSIZE_KB_4096 - default 0x80600000 if COREBOOT_ROMSIZE_KB_6144 - default 0x80800000 if COREBOOT_ROMSIZE_KB_8192 - default 0x80a00000 if COREBOOT_ROMSIZE_KB_10240 - default 0x80c00000 if COREBOOT_ROMSIZE_KB_12288 - default 0x81000000 if COREBOOT_ROMSIZE_KB_16384 - default 0x82000000 if COREBOOT_ROMSIZE_KB_32768 - default 0x84000000 if COREBOOT_ROMSIZE_KB_65536 + default 0x80020000
endif # BOARD_EMULATION_QEMU_RISCV diff --git a/src/mainboard/emulation/qemu-riscv/Makefile.mk b/src/mainboard/emulation/qemu-riscv/Makefile.mk index 1a8342d..e796c34 100644 --- a/src/mainboard/emulation/qemu-riscv/Makefile.mk +++ b/src/mainboard/emulation/qemu-riscv/Makefile.mk @@ -1,16 +1,17 @@ ## SPDX-License-Identifier: GPL-2.0-only
+bootblock-y += mainboard.c bootblock-y += uart.c bootblock-y += rom_media.c bootblock-y += clint.c +bootblock-y += cbmem.c +bootblock-y += romstage.c
-romstage-y += romstage.c -romstage-y += uart.c -romstage-y += rom_media.c -romstage-y += clint.c - +ramstage-y += mainboard.c ramstage-y += uart.c ramstage-y += rom_media.c ramstage-y += clint.c +ramstage-y += cbmem.c +ramstage-y += chip.c
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include diff --git a/src/mainboard/emulation/qemu-riscv/cbmem.c b/src/mainboard/emulation/qemu-riscv/cbmem.c new file mode 100644 index 0000000..f9b56bd --- /dev/null +++ b/src/mainboard/emulation/qemu-riscv/cbmem.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <cbmem.h> +#include <symbols.h> +#include <ramdetect.h> + +uintptr_t cbmem_top_chipset(void) +{ + //TODO get memory range from QEMUs FDT + return (uintptr_t)_dram + CONFIG_DRAM_SIZE_MB * MiB; +} diff --git a/src/mainboard/emulation/qemu-riscv/chip.c b/src/mainboard/emulation/qemu-riscv/chip.c new file mode 100644 index 0000000..5cec284 --- /dev/null +++ b/src/mainboard/emulation/qemu-riscv/chip.c @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> + +struct chip_operations mainboard_emulation_qemu_riscv_ops = { + .name = "QEMU RISC-V", +}; diff --git a/src/mainboard/emulation/qemu-riscv/devicetree.cb b/src/mainboard/emulation/qemu-riscv/devicetree.cb index 120af99..9de1b75 100644 --- a/src/mainboard/emulation/qemu-riscv/devicetree.cb +++ b/src/mainboard/emulation/qemu-riscv/devicetree.cb @@ -1,5 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only
-chip soc/ucb/riscv +chip mainboard/emulation/qemu-riscv device cpu_cluster 0 on end end diff --git a/src/mainboard/emulation/qemu-riscv/include/mainboard/addressmap.h b/src/mainboard/emulation/qemu-riscv/include/mainboard/addressmap.h index 27baeb7..ef048bc 100644 --- a/src/mainboard/emulation/qemu-riscv/include/mainboard/addressmap.h +++ b/src/mainboard/emulation/qemu-riscv/include/mainboard/addressmap.h @@ -4,4 +4,26 @@ #define QEMU_VIRT_PLIC 0x0c000000 #define QEMU_VIRT_UART0 0x10000000 #define QEMU_VIRT_VIRTIO 0x10001000 +#define QEMU_VIRT_FLASH 0x20000000 #define QEMU_VIRT_DRAM 0x80000000 + +//#define QEMU_VIRT_DEBUG 0x00000000 // size: 0x100 }, +//#define QEMU_VIRT_MROM 0x00001000 // size: 0xf000 }, +//#define QEMU_VIRT_TEST 0x00100000 // size: 0x1000 }, +//#define QEMU_VIRT_RTC 0x00101000 // size: 0x1000 }, +//#define QEMU_VIRT_CLINT 0x02000000 // size: 0x10000 }, +//#define QEMU_VIRT_ACLINT_SSWI 0x02F00000 // size: 0x4000 }, +//#define QEMU_VIRT_PCIE_PIO 0x03000000 // size: 0x10000 }, +//#define QEMU_VIRT_PLATFORM_BUS 0x04000000 // size: 0x2000000 }, +//#define QEMU_VIRT_PLIC 0x0c000000 // size: VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) }, +//#define QEMU_VIRT_APLIC_M 0x0c000000 // size: APLIC_SIZE(VIRT_CPUS_MAX) }, +//#define QEMU_VIRT_APLIC_S 0x0d000000 // size: APLIC_SIZE(VIRT_CPUS_MAX) }, +//#define QEMU_VIRT_UART0 0x10000000 // size: 0x100 }, +//#define QEMU_VIRT_VIRTIO 0x10001000 // size: 0x1000 }, +//#define QEMU_VIRT_FW_CFG 0x10100000 // size: 0x18 }, +//#define QEMU_VIRT_FLASH 0x20000000 // size: 0x4000000 }, +//#define QEMU_VIRT_IMSIC_M 0x24000000 // size: VIRT_IMSIC_MAX_SIZE }, +//#define QEMU_VIRT_IMSIC_S 0x28000000 // size: VIRT_IMSIC_MAX_SIZE }, +//#define QEMU_VIRT_PCIE_ECAM 0x30000000 // size: 0x10000000 }, +//#define QEMU_VIRT_PCIE_MMIO 0x40000000 // size: 0x40000000 }, +//#define QEMU_VIRT_DRAM 0x80000000 // size: 0x0 }, diff --git a/src/mainboard/emulation/qemu-riscv/mainboard.c b/src/mainboard/emulation/qemu-riscv/mainboard.c index f0f0740..12ce8df4 100644 --- a/src/mainboard/emulation/qemu-riscv/mainboard.c +++ b/src/mainboard/emulation/qemu-riscv/mainboard.c @@ -1,20 +1,22 @@ /* SPDX-License-Identifier: GPL-2.0-only */
+#include <cbmem.h> #include <console/console.h> +#include <console/uart.h> #include <device/device.h> #include <symbols.h> #include <ramdetect.h> +#include <bootblock_common.h>
static void mainboard_enable(struct device *dev) { - size_t dram_mb_detected; - if (!dev) { die("No dev0; die\n"); }
- dram_mb_detected = probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB); - ram_range(dev, 0, (uintptr_t)_dram, dram_mb_detected * MiB); + size_t dram_detected = (size_t)cbmem_top() - (size_t)_dram; + printk(BIOS_DEBUG, "Memory Configured = %zd MB\n", dram_detected); + ram_range(dev, 0, (uintptr_t)_dram, dram_detected); }
struct chip_operations mainboard_ops = { diff --git a/src/mainboard/emulation/qemu-riscv/memlayout.ld b/src/mainboard/emulation/qemu-riscv/memlayout.ld index 4fdeb9dc..29fe12c 100644 --- a/src/mainboard/emulation/qemu-riscv/memlayout.ld +++ b/src/mainboard/emulation/qemu-riscv/memlayout.ld @@ -4,28 +4,18 @@ #include <arch/header.ld> #include <mainboard/addressmap.h>
-// Stages start after CBFS in DRAM -#define STAGES_START (QEMU_VIRT_DRAM + CONFIG_ROM_SIZE) - SECTIONS { - // the virt target doesn't emulate flash and just puts the CBFS into DRAM. - // fake SRAM where CBFS resides. It's only done for better integration. - SRAM_START(QEMU_VIRT_DRAM) - BOOTBLOCK(QEMU_VIRT_DRAM, 64K) - // CBFS goes here - SRAM_END(STAGES_START) - DRAM_START(STAGES_START) + REGION(flash, QEMU_VIRT_FLASH, 32M, 0) \
-#if ENV_SEPARATE_ROMSTAGE - ROMSTAGE(STAGES_START, 128K) -#endif + DRAM_START(QEMU_VIRT_DRAM) + BOOTBLOCK(QEMU_VIRT_DRAM, 128K) #if ENV_RAMSTAGE - REGION(opensbi, STAGES_START, 128K, 4K) + REGION(opensbi, QEMU_VIRT_DRAM + 128K, 256K, 4K) #endif - PRERAM_CBMEM_CONSOLE(STAGES_START + 128K, 8K) - FMAP_CACHE(STAGES_START + 136K, 2K) - CBFS_MCACHE(STAGES_START + 138K, 8K) - RAMSTAGE(STAGES_START + 200K, 16M) - STACK(STAGES_START + 200K + 16M, 4K) + RAMSTAGE( QEMU_VIRT_DRAM + 128K + 256K, 2M) + PRERAM_CBMEM_CONSOLE(QEMU_VIRT_DRAM + 128K + 256K + 2M, 8K) + FMAP_CACHE( QEMU_VIRT_DRAM + 128K + 256K + 2M + 8K, 2K) + CBFS_MCACHE( QEMU_VIRT_DRAM + 128K + 256K + 2M + 8K + 2K, 10K) + STACK( QEMU_VIRT_DRAM + 128K + 256K + 2M + 8K + 2K + 10K, 4M) } diff --git a/src/mainboard/emulation/qemu-riscv/rom_media.c b/src/mainboard/emulation/qemu-riscv/rom_media.c index 15989f2..3c636ce 100644 --- a/src/mainboard/emulation/qemu-riscv/rom_media.c +++ b/src/mainboard/emulation/qemu-riscv/rom_media.c @@ -1,11 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <boot_device.h> #include <symbols.h> +#include <mainboard/addressmap.h>
-/* This assumes that the CBFS resides at start of dram, which is true for the - * default configuration. */ static const struct mem_region_device boot_dev = - MEM_REGION_DEV_RO_INIT(_sram, CONFIG_ROM_SIZE); + MEM_REGION_DEV_RO_INIT(QEMU_VIRT_FLASH, CONFIG_ROM_SIZE);
const struct region_device *boot_device_ro(void) { diff --git a/src/mainboard/emulation/qemu-riscv/romstage.c b/src/mainboard/emulation/qemu-riscv/romstage.c index 4a3ed83..02062ae 100644 --- a/src/mainboard/emulation/qemu-riscv/romstage.c +++ b/src/mainboard/emulation/qemu-riscv/romstage.c @@ -3,10 +3,10 @@ #include <cbmem.h> #include <console/console.h> #include <program_loading.h> +#include <romstage_common.h>
-void main(void) +void __noreturn romstage_main(void) { - console_init(); cbmem_initialize_empty(); run_ramstage(); } diff --git a/src/soc/ucb/riscv/cbmem.c b/src/soc/ucb/riscv/cbmem.c index 5c423a0..e49d517 100644 --- a/src/soc/ucb/riscv/cbmem.c +++ b/src/soc/ucb/riscv/cbmem.c @@ -6,5 +6,5 @@
uintptr_t cbmem_top_chipset(void) { - return (uintptr_t)_dram + (probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB) * MiB); + return (uintptr_t)_romstage + (CONFIG_COREBOOT_ROMSIZE_KB * KiB); }