Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81556?usp=email )
Change subject: mb/google/brox: Enable SAGv ......................................................................
mb/google/brox: Enable SAGv
Enable SaGv support for brox
BUG=None BRANCH=None TEST=Boot brox with SAGv enabled and verify in fsp debug logs
Change-Id: I80c44e7df1d75732c6982b27e44ecd6060b1b3f1 Signed-off-by: Ashish Kumar Mishra ashish.k.mishra@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/81556 Reviewed-by: Krishna P Bhat D krishna.p.bhat.d@intel.com Reviewed-by: Shelley Chen shchen@google.com Reviewed-by: Karthik Ramasubramanian kramasub@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb 1 file changed, 3 insertions(+), 0 deletions(-)
Approvals: Karthik Ramasubramanian: Looks good to me, approved build bot (Jenkins): Verified Krishna P Bhat D: Looks good to me, but someone else must approve Shelley Chen: Looks good to me, approved
diff --git a/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb b/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb index 9ed0602..f901db9 100644 --- a/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb +++ b/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb @@ -11,6 +11,9 @@ # EC memory map range is 0x900-0x9ff register "gen3_dec" = "0x00fc0901"
+ # Enable SAGv + register "sagv" = "SaGv_Enabled" + # S0ix enable register "s0ix_enable" = "1"