[S] Change in coreboot[master]: soc/intel/elkhartlake: Correct I2C base clock to 100 MHz

[Werner Zeh (Code Review)]

Attention is currently required from: Lean Sheng Tan.

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69305 )

Change subject: soc/intel/elkhartlake: Correct I2C base clock to 100 MHz
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soc/intel/elkhartlake: Correct I2C base clock to 100 MHz

According to measurements Elkhart Lake seems to drive the internal I2C
controllers with 100 MHz instead of the common 133 MHz. The datasheet
itself is quite vague on this definition, just one place mentions that
it is 100 MHz (register description for offset 0x94).

This patch changes the I2C controller base frequency to 100 MHz. The
verification was done by measuring the set up resulting I2C clock for
both 100 and 400 kHz.

Change-Id: I7c826bbb01b53e3661746e49f25441565068d1c2
Signed-off-by: Werner Zeh 
---
M src/soc/intel/elkhartlake/Kconfig
1 file changed, 20 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/69305/1

diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig
index 4343e85..8e3dc11 100644
--- a/src/soc/intel/elkhartlake/Kconfig
+++ b/src/soc/intel/elkhartlake/Kconfig
@@ -151,7 +151,7 @@

config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
    int
-	default 133
+	default 100

config SOC_INTEL_COMMON_BLOCK_GSPI_MAX
    int