Change in coreboot[master]: util: Add new memory part for brya boards

[Amanda Hwang (Code Review)]

Amanda Hwang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/51167 )

Change subject: util: Add new memory part for brya boards
......................................................................

util: Add new memory part for brya boards

Add memory part MT53E2G32D4NQ-046 to LP4x global list. Attributes
are derived from data sheets.

BUG=b:181378727
TEST=Compared generated SPD with data sheets and checked in SPD

Change-Id: Ic06e9d672a2d3db2b4ea12d15b462843c90db8f6
Signed-off-by: Amanda Huang 
---
A src/soc/intel/alderlake/spd/lp4x-spd-6.hex
M src/soc/intel/alderlake/spd/lp4x_spd_manifest.generated.txt
M util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt
3 files changed, 45 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/51167/1

diff --git a/src/soc/intel/alderlake/spd/lp4x-spd-6.hex b/src/soc/intel/alderlake/spd/lp4x-spd-6.hex
new file mode 100644
index 0000000..212dfca
--- /dev/null
+++ b/src/soc/intel/alderlake/spd/lp4x-spd-6.hex
@@ -0,0 +1,32 @@
+23 11 11 0E 16 29 F8 08 00 00 00 00 0A 01 00 00
+00 00 04 FF 92 54 05 00 87 00 90 A8 90 E0 0B F0
+05 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 E5 00 E0 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20
[phone] 20 20 20 20 20 20 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/soc/intel/alderlake/spd/lp4x_spd_manifest.generated.txt b/src/soc/intel/alderlake/spd/lp4x_spd_manifest.generated.txt
index f09a27f..0f7e93c 100644
--- a/src/soc/intel/alderlake/spd/lp4x_spd_manifest.generated.txt
+++ b/src/soc/intel/alderlake/spd/lp4x_spd_manifest.generated.txt
@@ -17,3 +17,4 @@
 H9HCNNNFBMBLPR-NEE,lp4x-spd-3.hex
 MT53D1G64D4NW-046 WT:A,lp4x-spd-4.hex
 MT53D512M64D4NW-046 WT:F,lp4x-spd-1.hex
+MT53E2G32D4NQ-046 WT:A,lp4x-spd-6.hex
diff --git a/util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt b/util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt
index ffb08c7..88c6661 100644
--- a/util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt
+++ b/util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt
@@ -229,6 +229,18 @@
                 "ranksPerChannel": 1,
                 "speedMbps": 4267
             }
+        },
+	{
+            "name": "MT53E2G32D4NQ-046 WT:A",
+            "attribs": {
+                "densityPerChannelGb": 16,
+                "banks": 8,
+                "channelsPerDie": 4,
+                "diesPerPackage": 1,
+                "bitWidthPerChannel": 16,
+                "ranksPerChannel": 2,
+                "speedMbps": 4267
+            }
         }
     ]
 }