Change in coreboot[master]: soc/intel/denverton_ns: Fix MRC_RW_CACHE

[Kyösti Mälkki (Code Review)]

Attention is currently required from: Mariusz Szafrański, Suresh Bellampalli, Vanessa Eusebio, Michal Motyl, Patrick Rudolph.
Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60091 )

Change subject: soc/intel/denverton_ns: Fix MRC_RW_CACHE
......................................................................

soc/intel/denverton_ns: Fix MRC_RW_CACHE

It is required to set WPD (Write Protect Disable) bit
to make it possible to use MRC_RW_CACHE region with
CACHE_MRC_SETTINGS=y.

Change-Id: Iacab44b00d08c9bdc18bc3bdcb88833634c0b02e
Signed-off-by: Kyösti Mälkki 
---
M src/soc/intel/denverton_ns/bootblock/bootblock.c
1 file changed, 2 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/60091/1

diff --git a/src/soc/intel/denverton_ns/bootblock/bootblock.c b/src/soc/intel/denverton_ns/bootblock/bootblock.c
index cb2503a..7f35123 100644
--- a/src/soc/intel/denverton_ns/bootblock/bootblock.c
+++ b/src/soc/intel/denverton_ns/bootblock/bootblock.c
@@ -12,6 +12,7 @@
 #include <spi-generic.h>
 #include <stdint.h>
 #include <console/console.h>
+#include <intelblocks/fast_spi.h>

const FSPT_UPD temp_ram_init_params = {
    .FspUpdHeader = {
@@ -84,6 +85,7 @@
 #if (CONFIG(CONSOLE_SERIAL))
    early_uart_init();
 #endif
+	fast_spi_early_init(DEFAULT_SPI_BASE);
 };

void bootblock_soc_init(void)